ZHCSKB9Q December   1999  – October 2019 UCC1895 , UCC2895 , UCC3895

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化应用示意图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  ADS (Adaptive Delay Set)
      2. 7.3.2  CS (Current Sense)
      3. 7.3.3  CT (Oscillator Timing Capacitor)
      4. 7.3.4  DELAB and DELCD (Delay Programming Between Complementary Outputs)
      5. 7.3.5  EAOUT, EAP, and EAN (Error Amplifier)
      6. 7.3.6  OUTA, OUTB, OUTC, and OUTD (Output MOSFET Drivers)
      7. 7.3.7  PGND (Power Ground)
      8. 7.3.8  RAMP (Inverting Input of the PWM Comparator)
      9. 7.3.9  REF (Voltage Reference)
      10. 7.3.10 RT (Oscillator Timing Resistor)
      11. 7.3.11 GND (Analog Ground)
      12. 7.3.12 SS/DISB (Soft Start/Disable)
      13. 7.3.13 SYNC (Oscillator Synchronization)
      14. 7.3.14 VDD (Chip Supply)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Programming DELAB, DELCD and the Adaptive Delay Set
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Power Loss Budget
        2. 8.2.2.2  Preliminary Transformer Calculations (T1)
        3. 8.2.2.3  QA, QB, QC, QD FET Selection
        4. 8.2.2.4  Selecting LS
        5. 8.2.2.5  Selecting Diodes DB and DC
        6. 8.2.2.6  Output Inductor Selection (LOUT)
        7. 8.2.2.7  Output Capacitance (COUT)
        8. 8.2.2.8  Select Rectifier Diodes
        9. 8.2.2.9  Input Capacitance (CIN)
        10. 8.2.2.10 Current Sense Network (CT, RCS, RR, DA)
          1. 8.2.2.10.1 Output Voltage Setpoint
          2. 8.2.2.10.2 Voltage Loop Compensation
          3. 8.2.2.10.3 Setting the Switching Frequency
          4. 8.2.2.10.4 Soft Start
          5. 8.2.2.10.5 Setting the Switching Delays
          6. 8.2.2.10.6 Setting the Slope Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
      2. 11.1.2 相关链接
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

5 Pin Configuration and Functions

PW AND DW PACKAGE DRAWINGS
(TOP VIEW)
UCC1895 UCC2895 UCC3895 po1_sw_dw_slus157.gif
N AND J PACKAGE DRAWINGS
(TOP VIEW)
UCC1895 UCC2895 UCC3895 po2_soic_slus157.gif
FN AND FK PACKAGE DRAWINGS
(TOP VIEW)
UCC1895 UCC2895 UCC3895 po3_q_l_slus157.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
ADS 11 I The adaptive-delay-set pin sets the ratio between the maximum and minimum programmed output delay dead time.
CS 12 I Current sense input for cycle-by-cycle current limiting and for over-current comparator.
CT 7 I Oscillator timing capacitor for programming the switching frequency. The UCC3895 oscillator charges CT via a programmed current.
DELAB 9 I The delay-programming between complementary-outputs pin, DELAB, programs the dead time between switching of output A and output B.
DELCD 10 I The delay-programming between complementary-outputs pin, DELCD, programs the dead time between switching of output C and output D.
EAOUT 2 I/O Error amplifier output.
EAP 20 I Non-inverting input to the error amplifier. Keep below 3.6 V for proper operation.
EAN 1 I Inverting input to the error amplifier. Keep below 3.6 V for proper operation.
GND 5 — Chip ground for all circuits except the output stages.
OUTA 18 O The four outputs are 100-mA complementary MOS drivers, and are optimized to drive FET driver circuits such as UCC27714 or gate drive transformers.
OUTB 17 O
OUTC 14 O
OUTD 13 O
PGND 16 — Output stage ground.
RAMP 3 I Inverting input of the PWM comparator.
REF 4 O 5-V, ±1.2%, 5-mA voltage reference. For best performance, bypass with a 0.1-μF low ESR, low ESL capacitor to ground. Do not use more than 4.7 μF of total capacitance on this pin.
RT 8 I Oscillator timing resistor for programming the switching frequency.
SS/DISB 19 I Soft-start and disable pin which combines the two independent functions.
SYNC 6 I/O The oscillator synchronization pin is bidirectional.
VDD 15 I The power supply input pin, VDD, must be bypassed with a minimum of a 1-μF low ESR, low ESL capacitor to ground. The addition of a 10-μF low ESR, low ESL between VDD and PGND is recommended.
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