The USB PLL block generates the clocks used to synchronize:

• The ULPI interface (60 MHz clock)
• The USB interface (depending on the USB data rate, 480 Mbps, 12 Mbps, or 1.5 Mbps)

TUSB1210 requires an external reference clock which is used as an input to the 480 MHz USB PLL block. Depending on the clock configuration, this reference clock can be provided either at REFCLK pin or at CLOCK pin. By default CLK pin is configured as an input.

Two clock configurations are possible:

• Input clock configuration (see Section 7.3.1.1.2)
• Output clock configuration (see Section 7.3.1.1.3)