ZHCSKX3 March 2020 PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1 , PCM6360-Q1
ADVANCE INFORMATION for pre-production products; subject to change without notice.
Certain events in the device may require host processor intervention and can be used to trigger interrupts to the host processor. Such event are an audio serial interface (ASI) bus error and input DC fault diagnostic faults. The device powers down the record channels if any faults are detected with the ASI bus error clocks, such as:
When an ASI bus clock error is detected, the device shuts down the record channel as quickly as possible. After all ASI bus clock errors are resolved, the device volume ramps back to its previous state to recover the record channel. During an ASI bus clock error, the internal interrupt request (IRQ) interrupt signal asserts low if the clock error interrupt mask register bit INT_MASK0[7], P0_R51_D7 is set low. The clock fault is also available for readback in the live fault status register bit INT_LIVE0, P1_R44 as well as latched to the fault status register bit INT_LTCH0, P0_R44, which is a read-only register. Reading the latched fault status register, INT_LTCH0, clears all latched fault statuses. The device can be additionally configured to route the internal IRQ interrupt signal on the GPIOx pins and also can be configured as an open-drain output so that these pins can be wire-ANDed to the open-drain interrupt outputs of other devices.
When an input DC fault event is detected, the internal IRQ signal is asserted if the interrupt mask registers INT_MASK1, P0_R42 and INT_MASK2, P0_R43 are configured appropriately to unmask all the desired fault diagnostics interrupts. Each input channel can be independently set for an interrupt mask. Table 44 and Table 45 list the mask settings available for the input DC diagnostics fault interrupts.
| P0_R42 : INT_MASK1 | INTERRUPT MASK REGISTER 1 FOR DC FAULTS DIAGNOSTIC INTERRUPTS |
|---|---|
| INT_MASK1[7] | Channel 1 input DC faults diagnostic interrupt mask and unmask register bit |
| INT_MASK1[6] | Channel 2 input DC faults diagnostic interrupt mask and unmask register bit |
| INT_MASK1[5] | Channel 3 input DC faults diagnostic interrupt mask and unmask register bit |
| INT_MASK1[4] | Channel 4 input DC faults diagnostic interrupt mask and unmask register bit |
| INT_MASK1[3] | Channel 5 input DC faults diagnostic interrupt mask and unmask register bit |
| INT_MASK1[2] | Channel 6 input DC faults diagnostic interrupt mask and unmask register bit |
| INT_MASK1[1] | Short to VBAT_IN (when VBAT_IN is lower than MICBIAS) fault interrupt mask and unmask register bit |
| INT_MASK1[0] | Reserved |
| P0_R43 : INT_MASK2 | INTERRUPT MASK REGISTER 2 FOR DC FAULTS DIAGNOSTIC INTERRUPTS |
|---|---|
| INT_MASK2[7] | Open input fault interrupt mask and unmask register bit for all channels |
| INT_MASK2[6] | Inputs shorted each other fault interrupt mask and unmask register bit for all channels |
| INT_MASK2[5] | IN1P input shorted to ground fault interrupt mask and unmask register bit for all channels |
| INT_MASK2[4] | IN1M input shorted to ground fault interrupt mask and unmask register bit for all channels |
| INT_MASK2[3] | IN1P input shorted to MICBIAS fault interrupt mask and unmask register bit for all channels |
| INT_MASK2[2] | IN1M input shorted to MICBIAS fault interrupt mask and unmask register bit for all channels |
| INT_MASK2[1] | IN1P input shorted to VBAT_IN fault interrupt mask and unmask register bit for all channels |
| INT_MASK2[0] | IN1M input shorted to VBAT_IN fault interrupt mask and unmask register bit for all channels |
The device supports the channel-specific input DC fault latched status registers for all channels from CH1_LTCH, P0_R46 to CH6_LTCH, P0_R51, which are read-only registers. The device also has a consolidated summary status register across channels for the input DC latched fault status register, CHx_LTCH, P0_R45 that the host can read to quickly know which channel fault has occurred. Reading the latched fault status registers, CH1_LTCH to CH6_LTCH, clears all the latched fault status including the summary status register, CHx_LTCH. Table 46 shows various input DC fault diagnostics status bits that are supported by the device.
| P0_R46 : CH1_LTCH | CHANNEL 1 INPUT FAULTS DIAGNOSTIC LATCHED STATUS |
|---|---|
| CH1_LTCH[7] | Channel 1 open input fault detection status bit (self-clearing bit) |
| CH1_LTCH[6] | Channel 1 inputs shorted together fault detection status bit (self-clearing bit) |
| CH1_LTCH[5] | Channel 1 IN1P input shorted to ground fault detection status bit (self-clearing bit) |
| CH1_LTCH[4] | Channel 1 IN1M input shorted to ground fault detection status bit (self-clearing bit) |
| CH1_LTCH[3] | Channel 1 IN1P input shorted to MICBIAS fault detection status bit (self-clearing bit) |
| CH1_LTCH[2] | Channel 1 IN1M input shorted to MICBIAS fault detection status bit (self-clearing bit) |
| CH1_LTCH[1] | Channel 1 IN1P input shorted to VBAT_IN fault detection status bit (self-clearing bit) |
| CH1_LTCH[0] | Channel 1 IN1M input shorted to VBAT_IN fault detection status bit (self-clearing bit) |
Similarly, the DC faults diagnostic latched status for input channel 2 to channel 6 can be monitored using the CH2_LTCH (P0_R47) to CH6_LTCH (P0_R51) registers, respectively.
The device GPIOx pins can be additionally configured to route the internal IRQ interrupt signal on the GPIOx pins and also can be configured as an open-drain output so that this pin can be wire-ANDed to the open-drain interrupt outputs of other devices.
The IRQ interrupt signal can either be configured as an active low or active high polarity by setting the INT_POL, P0_R40_D7 register bit. This signal can also be configured as a single pulse or a series of pulses by programming the INT_EVENT[1:0], P0_R40_D[6:5] register bits. If the interrupts are configured as a series of pulses, the events trigger the start of pulses that stop when the latched fault status register is read to determine the cause of the interrupt.
The device also supports read-only live status registers that determine if all the channels are powered up or down and if the device is in sleep mode or not. These status registers are located in P0_R118, DEV_STS0 and P0_R119, DEV_STS1.
The device has a GPIO1 multifunction pin that can be configured for a desired specific function. Additionally the PCM6x40-Q1 has two more GPIO pins and two GPI pins supported that can be used in the system for various other features. Table 47 shows all possible allocation of these multifunction pins for all the various features.
| ROW | PIN FUNCTION | GPIO1 | GPIO2 | GPIO3 | GPI1 | GPI2 |
|---|---|---|---|---|---|---|
| — | — | GPIO1_CFG
[4:0] |
GPIO2_CFG
[4:0] |
GPIO3_CFG
[4:0] |
GPI1_CFG[4:0] | GPI2_CFG[4:0] |
| — | — | P0_R33[7:4] | P0_R34[7:4] | P0_R35[7:4] | P0_R36[7:4] | P0_R37[7:4] |
| A | Pin disabled | S(1) | S (default) | S (default) | S (default) | S (default) |
| B | General-purpose output (GPO) | S | S | S | NS(2) | NS |
| C | Interrupt output (IRQ) | S (default) | S | S | NS | NS |
| D | Secondary ASI output (SDOUT2) | S | S | S | NS | NS |
| F | MiCBIAS on/off input (BIASEN) | S | S | S | S | S |
| G | General-purpose input (GPI) | S | S | S | S | S |
| H | Master clock input (MCLK) | S | S | S | S | S |
| I | ASI daisy-chain input (SDIN) | S | S | S | S | S |
Each GPIOx pin can be independently set for the desired drive configurations setting using the GPIOx_DRV[3:0] register bits. Table 48 lists the drive configuration settings.
| P0_R33_D[3:0] : GPIO1_DRV[3:0] | GPIO OUTPUT DRIVE CONFIGURATION SETTINGS FOR GPIO1 |
|---|---|
| 000 | The GPIO1 pin is set to high impedance (floated) |
| 001 | The GPIO1 pin is set to be driven active low or active high |
| 010 (default) | The GPIO1 pin is set to be driven active low or weak high (on-chip pullup) |
| 011 | The GPIO1 pin is set to be driven active low or Hi-Z (floated) |
| 100 | The GPIO1 pin is set to be driven weak low (on-chip pulldown) or active high |
| 101 | The GPIO1 pin is set to be driven Hi-Z (floated) or active high |
| 110 and 111 | Reserved (do not use these settings) |
Similarly, the GPIO2 and GPIO3 pins can be configured using the GPIO2_DRV(P0_R34) and GPIO3_DRV(P0_R35) register bits, respectively.
When configured as a general-purpose output (GPO), the GPIOx pin values can be driven by writing the GPIO_VAL P0_R38 registers. The GPIO_MON, P0_R39 register can be used to readback the status of the GPIOx and GPIx pins when configured as a general-purpose input (GPI).