ZHCSL04A March   2020  – July 2020 ISO1044

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions—8 Pins
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics - DC Specification
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Parametric Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CAN Bus States
      2. 8.3.2 Digital Inputs and Outputs: TXD (Input) and RXD (Output)
      3. 8.3.3 Protection Features
        1. 8.3.3.1 TXD Dominant Timeout (DTO)
        2. 8.3.3.2 Thermal Shutdown (TSD)
        3. 8.3.3.3 Undervoltage Lockout and Default State
        4. 8.3.3.4 Floating Pins
        5. 8.3.3.5 Unpowered Device
        6. 8.3.3.6 CAN Bus Short Circuit Current Limiting
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bus Loading, Length and Number of Nodes
        2. 9.2.2.2 CAN Termination
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6.10 Switching Characteristics

Typical specifications are at VCC1 = 3.3 V, VCC2 = 5 V, Min/Max are over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DEVICE SWITCHING CHARACTERISTICS
tPROP(LOOP1) Total loop delay, driver input TXD to receiver RXD, recessive to dominant See Figure 7-6 , RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 1.71 V ≤ VCC1 ≤ 1.89 V 150 203 ns
See Figure 7-6 , RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 2.25 V ≤ VCC1 ≤ 5.5 V 150 199 ns
tPROP(LOOP2) Total loop delay, driver input TXD to receiver RXD, dominant to recessive See Figure 7-6 , RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 1.71 V ≤ VCC1 ≤ 1.89 V 175 219 ns
See Figure 7-6 , RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 2.25 V ≤ VCC1 ≤ 5.5 V 175 212 ns
tUV_RE_ENABLE Re-enable time after Undervoltage event Time for device to return to normal operation from VCC1 or VCC2 under voltage event 300.0 µs
CMTI Common mode transient immunity TXD=VCC1 or GND1, VCM = 1200VPK , See Figure 7-9 85 kV/µs
DRIVER SWITCHING CHARACTERISTICS
tpHR Propagation delay time, Low-to-High TXD edge to driver recessive See Figure 7-3 , RL = 60 Ω and CL = 100 pF; input rise/fall time (10% to 90%) on TXD =1 ns 85 105 ns
tpLD Propagation delay time, High-to-Low TXD edge to driver dominant 70 105
tsk(p) pulse skew (|tpHR - tpLD|) 12.5
tR Differential output signal rise time 27
tF Differential output signal fall time 42
VSYM Driver symmetry (VO(CANH) + VO(CANL))/VCC See Figure 7-3  and Figure 9-3 , RTERM =60 Ω, CL =open, CSPLIT= 4.7nF, TXD= Dominant or receissive or toggling at 250 kHz, 1 MHz 0.9 1.1 V/V
tTXD_DTO Dominant time out See Figure 7-7 , RL = 60 Ω and CL = open 1.2 3.8 ms
RECEIVER SWITCHING CHARACTERISTICS
tpRH Propagation delay time, bus dominant-to-recessive input edge to RXD high output See Figure 7-5 , CL(RXD) = 15 pF,  90 130 ns
tpDL Propogation delay time, bus recessive-to-dominant input edge to RXD low output 71 110 ns
tR Output signal rise time(RXD) 1 ns
tF Output signal fall time(RXD) 1 ns
FD TIMING PARAMETERS
tBIT(BUS) Bit time on CAN bus output pins with tBIT(TXD) = 500 ns See Figure 7-6 , RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns 435.0 530.0 ns
Bit time on CAN bus output pins with tBIT(TXD) = 200 ns See Figure 7-6 , RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns 155.0 210.0 ns
tBIT(RXD) Bit time on RXD output pin with tBIT(TXD) = 500 ns See Figure 7-6 , RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns 400 550.0 ns
Bit time on RXD output pin with tBIT(TXD) = 200 ns See Figure 7-6 , RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns 120.0 220.0 ns
∆tREC Receiver timing symmetry with tBIT(TXD) = 500 ns See Figure 7-6 , RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; ΔtREC = tBIT(RXD) - tBIT(BUS) -65.0 40.0 ns
Receiver timing symmetry with tBIT(TXD) = 200 ns See Figure 7-6 , RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns;  ΔtREC = tBIT(RXD) - tBIT(BUS) -45.0 15.0 ns
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