The device generates an internal 1.21-V bandgap reference that is utilized throughout the various control logic blocks. This is the voltage present on the REFCAP and SS/TR pins during steady state operation. This voltage is divided down to 0.604 V to produce the reference for the error amplifier. The error amplifier reference is measured at the COMP pin to account for offsets in the error amplifier and maintains regulation within ±1.5% across line, load, temperature, and TID (or ±1.7% for the SHP option) as shown in the Specifications. A 470-nF capacitor to ground is required at the REFCAP pin for proper electrical operation as well as to ensure robust SET performance of the device.