ZHCSL68C April   2017  – December 2020 TPS7A84A

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: General
    6. 6.6 Electrical Characteristics: TPS7A8400A
    7. 6.7 Electrical Characteristics: TPS7A8401A
    8. 6.8 Typical Characteristics: TPS7A8400A
    9. 6.9 Typical Characteristics: TPS7A8401A
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Regulation Features
        1. 7.3.1.1 DC Regulation
        2. 7.3.1.2 AC and Transient Response
      2. 7.3.2 System Start-Up Features
        1. 7.3.2.1 Programmable Soft Start (NR/SS)
        2. 7.3.2.2 Internal Sequencing
          1. 7.3.2.2.1 Enable (EN)
          2. 7.3.2.2.2 Undervoltage Lockout (UVLO) Control
          3. 7.3.2.2.3 Active Discharge
        3. 7.3.2.3 Power-Good Output (PG)
      3. 7.3.3 Internal Protection Features
        1. 7.3.3.1 Foldback Current Limit (ICL)
        2. 7.3.3.2 Thermal Protection (Tsd)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Regulation
      2. 7.4.2 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Component Selection
        1. 8.1.1.1 Adjustable Operation
        2. 8.1.1.2 ANY-OUT Programmable Output Voltage
        3. 8.1.1.3 ANY-OUT Operation
        4. 8.1.1.4 Increasing ANY-OUT Resolution for LILO Conditions
        5. 8.1.1.5 Current Sharing
        6. 8.1.1.6 Recommended Capacitor Types
        7. 8.1.1.7 Input and Output Capacitor Requirements (CIN and COUT)
        8. 8.1.1.8 Feed-Forward Capacitor (CFF)
        9. 8.1.1.9 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
      2. 8.1.2 Start-Up
        1. 8.1.2.1 Circuit Soft-Start Control (NR/SS)
          1. 8.1.2.1.1 Inrush Current
        2. 8.1.2.2 Undervoltage Lockout (UVLO)
        3. 8.1.2.3 Power-Good (PG) Function
      3. 8.1.3 AC and Transient Performance
        1. 8.1.3.1 Power-Supply Rejection Ratio (PSRR)
        2. 8.1.3.2 Output Voltage Noise
        3. 8.1.3.3 Optimizing Noise and PSRR
          1. 8.1.3.3.1 Charge Pump Noise
        4. 8.1.3.4 Load Transient Response
      4. 8.1.4 DC Performance
        1. 8.1.4.1 Output Voltage Accuracy (VOUT)
        2. 8.1.4.2 Dropout Voltage (VDO)
          1. 8.1.4.2.1 Behavior When Transitioning From Dropout Into Regulation
      5. 8.1.5 Sequencing Requirements
      6. 8.1.6 Negatively Biased Output
      7. 8.1.7 Reverse Current Protection
      8. 8.1.8 Power Dissipation (PD)
        1. 8.1.8.1 Estimating Junction Temperature
        2. 8.1.8.2 Recommended Area for Continuous Operation (RACO)
    2. 8.2 Typical Applications
      1. 8.2.1 Low-Input, Low-Output (LILO) Voltage Conditions
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Models
        2. 11.1.1.2 Spice Models
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表

8.1.3.4 Load Transient Response

The load-step transient response is the output voltage response by the LDO to a step in load current, whereby output voltage regulation is maintained. There are two key transitions during a load transient response: the transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in Figure 8-9 are broken down in this section and are described in Table 8-11. Regions A, E, and H are where the output voltage is in steady-state.

GUID-261B9FD3-D2B1-4BD8-84CE-5E2BA290593D-low.gifFigure 8-9 Load Transient Waveform
Table 8-11 Load Transient Waveform Description
REGION DESCRIPTION COMMENT
A Regulation Regulation
B Output current ramping Initial voltage dip is a result of the depletion of the output capacitor charge.
C LDO responding to transient Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage regulation.
D Reaching thermal equilibrium At high load currents the LDO takes some time to heat up. During this time the output voltage changes slightly.
E Regulation Regulation
F Output current ramping Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to increase.
G LDO responding to transient Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load discharging the output capacitor.
H Regulation Regulation

The transient response peaks (VOUT(max) and VOUT(min)) are improved by using more output capacitance; however, doing so slows down the recovery time (Wrise and Wfall). Figure 8-10 illustrates these parameters during a load transient, with a given pulse duration (PW) and current levels (IOUT(LO) and IOUT(HI)).

GUID-11D5234A-B4A2-46FC-8C0A-952FA2CB51D9-low.gifFigure 8-10 Simplified Load Transient Waveform
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |