The modulator generates a bitstream that has to be processed by a digital filter to obtain a digital word similar to a conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, as shown in Equation 2, built with minimal effort and hardware, is a sinc³-type filter:

Equation 2.

This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-order modulator. All characterization in this document is done with a sinc³ filter with an oversampling ratio (OSR) of 256 and an output word width of 16 bits, unless specified otherwise. The measured effective number of bits (ENOB) as a function of the OSR is illustrated in Figure 8-3 of the Section 8.2 section.

A delta sigma modulator filter calculator is available for download at www.ti.com that aids in the filter design and selecting the right OSR and filter-order to achieve the desired output resolution and filter response time.

An example code for implementing a sinc³ filter in an FPGA is discussed in the Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications application note, available for download at www.ti.com.