- For the ideal diode stage, connect A, DGATE and C pins of LM74810-Q1 close to the MOSFET's SOURCE, GATE and DRAIN pins.
For the load disconnect stage, connect HGATE and OUT pins of LM74810-Q1 close to the MOSFET's GATE and SOURCE pins.
- The high current path of for this solution is through the MOSFET, therefore it is important to use thick and short traces for source and drain of the MOSFET to minimize resistive losses.
The DGATE pin of the LM74810-Q1 must be connected to the MOSFET GATE with short trace.
Place transient suppression components close to LM74810-Q1.
Place the decopuling capacitor, CVS close to VS pin and chip GND.
- The charge pump capacitor across CAP and VS pins must be kept away from the MOSFET to lower the thermal effects on the capacitance value.
- Obtaining acceptable performance with alternate
layout schemes is possible, however the layout shown in the Layout Example is intended as a guideline and to produce
good results.