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ZHCSLC3B may 2020 – april 2023 TPD3S713-Q1 , TPD3S713A-Q1

PRODUCTION DATA

6.6 Switching Characteristics

Unless otherwise noted, –40°C ≤ T_J ≤ 125°C and 4.5 V ≤ V_(IN) ≤ 5.5 V, V_(EN) = V_(INT1) = V_{(ILIM_SEL)} = V_(IN), V_(INT2) = GND, R_(FAULT) = 10 kΩ, R_(IMON) = 2.55 kΩ, R_{(ILIM_HI)} = 52.3 kΩ. Positive currents are into pins. Typical values are at T_J = 25°C. All voltages are with respect to GND.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_r	BUS voltage rise time	V_(IN) = 5 V, C_(L) = 1 µF, R_(L) = 100 Ω	1.05	1.75	3.1	ms
t_f	BUS voltage fall time	V_(IN) = 5 V, C_(L) = 1 µF, R_(L) = 100 Ω	0.27	0.47	0.82	ms
t_on	BUS voltage turn-on time	V_(IN) = 5 V, C_(L) = 1 µF, R_(L) = 100 Ω		7.5	11	ms
t_off	BUS voltage turn-off time	V_(IN) = 5 V, C_(L) = 1 µF, R_(L) = 100 Ω		2.7	5	ms
t_{(DCHG_S)}	Discharge hold time (ILIM_SEL change)	Time V_(OUT) < 0.7V	1.1	2	2.9	s
t_(IOS)	BUS short-circuit response time⁽¹⁾	V_(IN) = 5 V, R_(SHORT) = 50 mΩ		2		µs
t_{(OC_BUS_FAULT)}	BUS FAULT deglitch time	Bidirectional deglitch applicable to current-limit condition only (no deglitch assertion for OTSD)	5.5	8.5	11.5	ms
t_pd	Analog switch propagation delay ⁽¹⁾	V_(IN) = 5 V		0.14		ns
t_(SK)	Analog switch skew between opposite transitions of the same port (t_PHL – t_PLH) ⁽¹⁾	V_(IN) = 5 V		0.02		ns
t_{(OV_Data)}	DP_IN and DM_IN overvoltage protection response time			5		µs
t_{(OV_BUS)}	BUS overvoltage protection response time			0.3		µs
t_{(OV_Data_FAULT)}	DP_IN and DM_IN FAULT-asserted degltich time		11	16	23	ms
	BUS FAULT-asserted degltich time		11	16	23	ms

(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.