Figure 8-31 shows the simplified block diagram related with the VDD startup function of UCC28782, and Figure 8-32 addresses the startup sequence. The detailed description on the startup waveforms is :

1. Time interval A: The UVLO circuit commands the two internal power-path switches (Q_DDS and Q_DDP) to close the connections between SWS, VDD, and P13 pins through two serial current-limiting resistors (R_DDS and R_DDP). The depletion-mode MOSFET (Q_S) starts sourcing charge current (I_SWS) safely from the high-voltage switch-node voltage (V_SW) to the VDD capacitor (C_VDD). Before V_VDD reaches 1.8 V, I_SWS is limited by the high-resistance R_DDS of 5 kΩ to prevent potential device damage if C_VDD or VDD pin is shorted to ground.
2. Time interval B: After V_VDD rises above 1.8 V, R_DDS is reduced to a smaller resistance of 0.5 kΩ. I_SWS is increased to charge C_VDD faster. The maximum charge current during VDD startup can be quantified by Equation 8.
3. Time interval C: As V_VDD reaches V_VDD(ON) of 17 V, the ULVO circuit turns-off Q_DDS to disconnect the source pin of Q_S to C_VDD, and turns-off Q_DDP to break the gate-to-source connection of Q_S, so Q_S loses its current-charge capability. V_VDD then starts to drop, because the 5-V regulator on REF pin starts to charge up the reference capacitor (C_REF) to 5 V, for which the maximum charge current (I_SE(REF)) is self-limited at around 17 mA. After V_REF is settled, the UVLO circuit turns-on another power-path switch (Q_P13), so an internal 13-V regulator is connected to the P13 pin. The voltage on the P13 pin capacitor (C_P13) starts to be discharged by the regulator.
4. Time interval D: While discharging the recommended 1 µF on C_P13 , the sink current of the 13-V regulator (I_P13(START)) is self-limited at around 2.2 mA, so it takes longer than 10 μs to settle to 13 V. If V_P13 reaches 13 V in less than 10 μs, the P13 pin open fault is triggered to protect the device. Once V_P13 has settled to 13 V without the fault event, RUN pin goes high and UCC28782 enters a run state with I_VDD = I_RUN.
5. Time interval E: There is a minimum 2.2-μs delay from RUN going high to PWML starting to switch in order to wake-up the gate driver and UCC28782. In this interval, the 2.8-Ω power path switch between the P13 pin and the S13 pin is enabled, so the S13-pin decoupling capacitor (C_S13) is charged up and the charge current is supplied from C_P13 and the P13 regulator. If 2.2-μs delay is timed out before V_S13 reaches to the 10-V power good threshold (V_{S13_OK}), the PWML switching instance will be further delayed.
6. Time interval F: This is the soft-start region of peak magnetizing current. The first purpose is to limit the supply current if the output is short. The second purpose is to push the switching frequency higher than the audible frequency range during repetitive startup situations. At the beginning of V_O soft-start, the peak current is limited by two V_CST thresholds. The first V_CST startup threshold (V_CST(SM1)) is clamped at 0.2 V and the following second threshold (V_CST(SM2)) is 0.5 V. When V_CST = V_CST(SM1), PWMH is disabled if the sampled VS pin voltage (V_VS) < 0.28 V, and the first five PWML pulses are forced to stay at this current level. After the sampled V_VS exceeds 0.28 V and the first five PWML pulses are generated, the peak current threshold changes from V_CST(SM1) to V_CST(SM2). In case of the inability to build up V_O with V_CST(SM1) at the beginning of the V_O soft-start due to excessively large output capacitor and/or constant-current output load, there is an internal time-out of 0.7 ms to force V_CST to switch to V_CST(SM2). At this moment, the BIN-pin capacitor voltage increases with V_O proportionally. If V_BIN is less than the 2.2-V UVLO threshold (VBIN(ON)), the bias switching regulator is disabled.
7. Time interval G: When V_BIN is higher than 2.2 V, the bias switching regulator enters into the boost switching mode, and starts to build up the V_VDD toward the 18.5-V regulation level.
8. Time interval H: When V_VS rises above 0.5 V, V_CST is allowed to reach V_CST(MAX) , so the ramp rate of V_O startup becomes faster. When PWML is in a high state, I_VDD can be larger than I_RUN, because the 5-V regulator provides the line-sensing current pulse (I_VSL) on the VS pin to sense V_BULK condition.
9. Time interval I: Higher V_BIN results in a lower switching frequency of the bias regulator, because more energy in the boost inductor (L_B) is transferred to C_VDD every switching cycle.
10. Time interval J: When V_BIN increases above the 15-V boost disable threshold, the V_VDD starts to decay back to the rectified auxiliary winding voltage minus the forward voltage drop of the boost diode (D_B). Also, when V_O gets close to the target regulation level, V_CST starts to reduce from V_CST(MAX).
11. Time interval K: V_O and V_CST settle, and the auxiliary winding takes over the VDD supply.

Figure 8-31 Functional Startup Block Diagram

Figure 8-32 Startup Timing Waveforms