UCC28782 integrates two control concepts to benefit high-efficiency operation: peak current-mode control and burst-ripple control. The peak current loop in AAM can be analyzed based on the linear control theory, so the compensation target is to obtain enough phase margin and gain margin for the given small-signal characteristic of an active clamp flyback converter. For Transition-Mode operation, the power stage can be modeled as a voltage-controlled current source charging an output capacitor (C_O) with an equivalent-series resistance (R_Co) and the output load (R_O) as shown in Figure 9-2. The first-order plant characteristic and high switching frequency operation in AAM make the peak current loop easier to stabilize than ABM.

Figure 9-2 Small-Signal Model of ACF in AAM Loop

The adaptive burst mode (ABM) uses ripple-based control, so the linear control theory for AAM cannot be applied. As illustrated in Figure 8-4, the internal ramp compensation feature of UCC28782 stabilizes the ABM control loop, so the external compensation network can be simplified.

Figure 9-3 Compensation Network, H_v(s)

The transfer function from I_FB to V_O guides the pole/zero placement of the general secondary-side compensation network in Figure 9-3. In the primary-side control circuitry, two poles at ω_FB and ω_OPTO introduce phase-delay on I_FB. ω_FB pole is formed by the external filter capacitor C_FB and the parallel resistance of the internal R_FBI and the external current-limiting resistor (R_FB). ω_OPTO pole is formed by the parasitic capacitance of the optocoupler output (C_OPTO) and the series resistance of R_FBI and R_FB. For C_FB = 220 pF, R_FBI = 8 KΩ, and R_FB = 20 KΩ, the delay effect of ω_FB pole located at 139 kHz is negligible. C_OPTO is in the range of a few nF contributed by the Miller effect of the collector-to-base capacitance of the BJT in the optocoupler output, so ω_OPTO pole is located at less than 10 kHz. If the control loop bandwidth needs to be designed at higher frequency for a faster transient response, the phase delay effect of ω_OPTO on the stability margin must be taken into account. Therefore, an RC network (R_DIFF and C_DIFF) in parallel with R_BIAS1 is used to compensate the phase-delay of the optocoupler, which introduces an extra pole/zero pair located at ω_P1 and ω_Z1 respectively. The basic design guide is to place the ω_Z1 zero close to the ω_OPTO pole, and to place ω_P1 pole away from highest f_BUR. On the other hand, if the stability margin and transient response are sufficient to meet the requirements without R_DIFF and C_DIFF, then these two components are optional for UCC28782.

Equation 56.

Equation 57.

Equation 58.

Equation 59.

Equation 60.

Equation 61.

The step-by-step design procedure of the compensator without R_DIFF and C_DIFF is:

1. R_FB selection needs to consider both the output voltage regulation and compensation challenge on the low-frequency pole at ω_OPTO. R_FB should be less than the maximum value of 28 kΩ to provide a sufficient feedback current of 95 μA for the output voltage regulation in SBP2 mode, under the worst-case V_FB(REG) and R_FBI. However, R_FB = 28 kΩ and C_OPTO = 2 nF result in an ω_OPTO pole located at 2.8 kHz. This low-frequency pole may reduce phase margin at the cross-over frequency. If the control bandwidth is around this frequency range, R_FB value should be designed even lower to move the pole to a higher frequency.
   Equation 62.
2. R_BIAS1 is determined based on a given current transfer ratio (CTR) of the optocoupler, ΔV_O(ABM), and target 4~5 μA of ΔI_FB as example. At collector currents less than 100 μA, the CTR of most optocouplers can be as low as 10%, or 0.1 (used in this example), although some high performance devices can have higher CTR.
   Equation 63.
3. R_INT selection is not designed for the small-signal compensation, but to resolve the slow large-signal response of the shunt regulator. Specifically, after a step-down load change from heavy load to no load occurs, the output voltage overshoot and the long settling time forces ATL431 to reduce the cathode voltage continuously by the integrator configuration until the output voltage gets back to normal regulation level. If the load step-up transient happens before the output voltage is settled from the previous load step-down event, the low voltage across ATL431 becomes the initial voltage level for the integrator to move to a new steady-state. Since the time for ATL431 to move from lower voltage to a high voltage delays i_FB reduction, the controller response from SBP mode to AAM mode is delayed as well, which slows down the energy delivery to the output and results in a large voltage undershoot.
   To resolve this problem, R_INT behaves like a current-limiting resistor for C_INT, which slows down the reduction of the cathode voltage of ATL431. R_INT needs to be adjusted based on the voltage undershoot requirement under the highest repetitive rate of load change.