Minimize stray capacitance at the VS pin to reduce the time-delay effect on ZVS control.

• Avoid putting GND plane under VS pin to reduce parasitic capacitance. This can be accomplished by putting a cutout in the ground plane below this pin pad and the tracks an pads of components connected to VS. minimize the track length of the VS net.
• Do not run other tracks or planes over or under the VS net.
• Do not run other tracks or planes under R_VS1 and R_VS2.