ZHCSLK6A July   2021  – December 2021 TPS1HC100-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Recommended Connections for Unused Pins
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SNS Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Accurate Current Sense
      2. 8.3.2 Programmable Current Limit
        1. 8.3.2.1 Capacitive Charging
      3. 8.3.3 Inductive-Load Switching-Off Clamp
      4. 8.3.4 Full Protections and Diagnostics
        1. 8.3.4.1  Short-Circuit and Overload Protection
        2. 8.3.4.2  Open-Load and Short-to-Battery Detection
        3. 8.3.4.3  Short-to-Battery Detection
        4. 8.3.4.4  Reverse-Polarity and Battery Protection
        5. 8.3.4.5  Latch-Off Mode
        6. 8.3.4.6  Thermal Protection Behavior
        7. 8.3.4.7  UVLO Protection
        8. 8.3.4.8  Loss of GND Protection
        9. 8.3.4.9  Loss of Power Supply Protection
        10. 8.3.4.10 Reverse Current Protection
        11. 8.3.4.11 Protection for MCU I/Os
      5. 8.3.5 Diagnostic Enable Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Working Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Dynamically Changing Current Limit
        2. 9.2.2.2 AEC Q100-012 Test Grade A Certification
        3. 9.2.2.3 EMC Transient Disturbances Test
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Without a GND Network
      2. 11.2.2 With a GND Network
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

6.6 SNS Timing Characteristics

VBB = 6 V to 18 V, TJ = -40°C to +150°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SNS TIMING - CURRENT SENSE
tSNSION1 Settling time from rising edge of DIA_EN
50% of VDIA_EN to 90% of settled ISNS		 VENx= 5 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ, IL = 1A		 30 µs
tSNSION1 Settling time from rising edge of DIA_EN
50% of VDIA_EN to 90% of settled ISNS		 VEN = 5 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ, IL = 30 mA		 30 µs
tSNSION2 Settling time from rising edge of EN and DIA_EN
50% of VDIA_EN  VEN to 90% of settled ISNS		 VEN = VDIA_EN = 0 V to 5 V
VBB = 13.5V RSNS = 1 kΩ, RLOAD = 10Ω		 150 µs
tSNSION3 Settling time from rising edge of EN with DIA_EN HI;
50% of VDIA_EN  VEN to 90% of settled ISNS		 VEN = 0 V to 5 V, VDIA_EN = 5 V VBB = 13.5V
RSNS = 1 kΩ, RLOAD = 10Ω		 150 µs
tSNSIOFF Settling time from falling edge of DIA_EN VEN = 5 V, VDIA_EN = 5 V to 0 V  VBB = 13.5V
RSNS = 1 kΩ, RL = 10 Ω		 20 µs
tSETTLEH Settling time from rising edge of load step VEN = 5 V, VDIA_EN = 5 V
RSNS = 1 kΩ, IOUT = 0.5 A to 3 A 		 20 µs
tSETTLEL Settling time from falling edge of load step VEN = 5 V, VDIA_EN = 5 V
RSNS = 1 kΩ, IOUT = 3 A to 0.5 A		 20 µs
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