ZHCSLN9A October   2020  – May 2021 DAC61402 , DAC81402

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: Write, IOVDD: 1.7 V to 2.7 V
    7. 7.7  Timing Requirements: Write, IOVDD: 2.7 V to 5.5 V
    8. 7.8  Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 1.7 V to 2.7 V
    9. 7.9  Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 1.7 V to 2.7 V
    10. 7.10 Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 2.7 V to 5.5 V
    11. 7.11 Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 2.7 V to 5.5 V
    12. 7.12 Timing Diagrams
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 R-2R Ladder DAC
      2. 8.3.2 Programmable-Gain Output Buffer
        1. 8.3.2.1 Sense Pins
      3. 8.3.3 DAC Register Structure
        1. 8.3.3.1 DAC Output Update
          1. 8.3.3.1.1 Synchronous Update
          2. 8.3.3.1.2 Asynchronous Update
        2. 8.3.3.2 Broadcast DAC Register
        3. 8.3.3.3 Clear DAC Operation
      4. 8.3.4 Internal Reference
      5. 8.3.5 Power-On Reset (POR)
        1. 8.3.5.1 Hardware Reset
        2. 8.3.5.2 Software Reset
      6. 8.3.6 Thermal Alarm
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Stand-Alone Operation
      2. 8.5.2 Daisy-Chain Operation
      3. 8.5.3 Frame Error Checking
    6. 8.6 Register Map
      1. 8.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 8.6.2  DEVICEID Register (address = 01h) [reset = 0A70h or 0930h]
      3. 8.6.3  STATUS Register (address = 02h) [reset = 0000h]
      4. 8.6.4  SPICONFIG Register (address = 03h) [reset = 0AA4h]
      5. 8.6.5  GENCONFIG Register (address = 04h) [reset = 4000h]
      6. 8.6.6  BRDCONFIG Register (address = 05h) [reset = 000Fh]
      7. 8.6.7  SYNCCONFIG Register (address = 06h) [reset = 0000h]
      8. 8.6.8  DACPWDWN Register (address = 09h) [reset = FFFFh]
      9. 8.6.9  DACRANGE Register (address = 0Ah) [reset = 0000h]
      10. 8.6.10 TRIGGER Register (address = 0Eh) [reset = 0000h]
      11. 8.6.11 BRDCAST Register (address = 0Fh) [reset = 0000h]
      12. 8.6.12 DACn Register (address = 11h to 12h) [reset = 0000h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

6 Pin Configuration and Functions

Figure 6-1 RHB (32-pin VQFN) Package, Top View
Table 6-1 Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
1 NC — No connection.
2 NC — No connection.
3 NC — No connection.
4 NC — No connection.
5 SENSENA Input Channel-A sense pin for the negative voltage output load connection.
6 SENSEPA Input Channel-A sense pin for the positive voltage output load connection.
7 CCOMPA Input Channel-A external compensation capacitor connection pin.
The addition of an external capacitor improves the output buffer stability with high capacitive loads at the OUTA pin by reducing the bandwidth of the output amplifier at the expense of increased settling time.
8 OUTA Output Channel-A analog output voltage.
9 SDO Output Serial interface data output.
The SDO pin must be enabled before operation by setting the SDO-EN bit. Data are clocked out of the input shift register on either rising or falling edges of the SCLK pin as specified by the FSDO bit (rising edge by default).
10 SCLK Input Serial interface clock.
11 SDIN Input Serial interface data input. Data are clocked into the input shift register on each falling edge of the SCLK pin.
12 SYNC Input Active low serial data enable. This input is the frame synchronization signal for the serial data. The serial serial interface input shift register is enabled when SYNC is low.
13 LDAC Input Active low synchronization signal. The DAC outputs of those channels configured in synchronous mode are updated simultaneously when the LDAC pin is low. Connect to IOVDD if unused.
14 GND Ground Digital ground reference point.
15 IOVDD Power IO supply voltage. This pin sets the digital I/O operating voltage for the device.
16 CLR Input Active-low clear input. Logic low on this pin clears all outputs to their clear code. Connect to IOVDD if unused.
17 OUTB Output Channel-B analog output voltage.
18 CCOMPB Input Channel-B external compensation capacitor connection pin.
The addition of an external capacitor improves the output buffer stability with high capacitive loads at the OUTB pin by reducing the bandwidth of the output amplifier at the expense of increased settling time.
19 SENSEPB Input Channel-B sense pin for the positive voltage output load connection.
20 SENSENB Input Channel-B sense pin for the negative voltage output load connection.
21 NC — No connection.
22 NC — No connection.
23 NC — No connection.
24 NC — No connection.
25 REFGND Ground Ground reference point for the internal reference.
26 REFIO Input/Output Reference input to the device when operating with an external reference. Reference output voltage pin when using the internal reference. Connect a 150-nF capacitor to ground.
27 AVSS Power Output buffers negative supply voltage.
28 AVDD Power Output buffers positive supply voltage.
29 AGND Ground Analog ground reference point.
30 DVDD Power Digital and analog supply voltage.
31 FAULT Output FAULT is an open-drain, fault-condition output. An external 10-kΩ pullup resistor to a voltage no higher than IOVDD is required.
32 RST Input Active-low reset input. Logic low on this pin causes the device to issue a power-on-reset event.
Thermal Pad Thermal pad — The thermal pad is located on the package underside. The thermal pad should be connected to any internal PCB ground plane through multiple vias for good thermal performance.
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