ZHCSLN9A October   2020  – May 2021 DAC61402 , DAC81402

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: Write, IOVDD: 1.7 V to 2.7 V
    7. 7.7  Timing Requirements: Write, IOVDD: 2.7 V to 5.5 V
    8. 7.8  Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 1.7 V to 2.7 V
    9. 7.9  Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 1.7 V to 2.7 V
    10. 7.10 Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 2.7 V to 5.5 V
    11. 7.11 Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 2.7 V to 5.5 V
    12. 7.12 Timing Diagrams
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 R-2R Ladder DAC
      2. 8.3.2 Programmable-Gain Output Buffer
        1. 8.3.2.1 Sense Pins
      3. 8.3.3 DAC Register Structure
        1. 8.3.3.1 DAC Output Update
          1. 8.3.3.1.1 Synchronous Update
          2. 8.3.3.1.2 Asynchronous Update
        2. 8.3.3.2 Broadcast DAC Register
        3. 8.3.3.3 Clear DAC Operation
      4. 8.3.4 Internal Reference
      5. 8.3.5 Power-On Reset (POR)
        1. 8.3.5.1 Hardware Reset
        2. 8.3.5.2 Software Reset
      6. 8.3.6 Thermal Alarm
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Stand-Alone Operation
      2. 8.5.2 Daisy-Chain Operation
      3. 8.5.3 Frame Error Checking
    6. 8.6 Register Map
      1. 8.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 8.6.2  DEVICEID Register (address = 01h) [reset = 0A70h or 0930h]
      3. 8.6.3  STATUS Register (address = 02h) [reset = 0000h]
      4. 8.6.4  SPICONFIG Register (address = 03h) [reset = 0AA4h]
      5. 8.6.5  GENCONFIG Register (address = 04h) [reset = 4000h]
      6. 8.6.6  BRDCONFIG Register (address = 05h) [reset = 000Fh]
      7. 8.6.7  SYNCCONFIG Register (address = 06h) [reset = 0000h]
      8. 8.6.8  DACPWDWN Register (address = 09h) [reset = FFFFh]
      9. 8.6.9  DACRANGE Register (address = 0Ah) [reset = 0000h]
      10. 8.6.10 TRIGGER Register (address = 0Eh) [reset = 0000h]
      11. 8.6.11 BRDCAST Register (address = 0Fh) [reset = 0000h]
      12. 8.6.12 DACn Register (address = 11h to 12h) [reset = 0000h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

8.5.3 Frame Error Checking

If the device is used in a noisy environment, error checking can be used to check the integrity of SPI data communication between the device and the host processor. This feature is enabled by setting the CRC-EN bit.

The error checking scheme is based on the CRC-8-ATM (HEC) polynomial: x8 + x2 + x + 1 (that is, 100000111). When error checking is enabled, the serial interface access cycle width is 32 bits. The normal 24-bit SPI data are appended with an 8-bit CRC polynomial by the host processor before feeding the data to the device. In all serial interface readback operations, the CRC polynomial is output on the SDO pin as part of the 32-bit cycle.

Table 8-4 Error Checking Serial Interface Access Cycle
BITFIELDDESCRIPTION
31RWIdentifies the communication as a read or write command to the address register.
R/W = 0 sets a write operation.
R/W = 1 sets a read operation.
30CRC-ERRORReserved bit. Set to zero.
29-24A[5:0]Register address. Specifies the register to be accessed during the read or write operation.
23-8DI[15:0]Data cycle bits.
If a write command, the data cycle bits are the values to be written to the register with address A[5:0].
If a read command, the data cycle bits are don't care values.
7-0CRC8-bit CRC polynomial.

The device decodes the 32-bit access cycle to compute the CRC remainder on SYNC rising edges. If no error exists, the CRC remainder is zero and data are accepted by the device.

A write operation failing the CRC check causes the data to be ignored by the device. After the write command, a second access cycle can be issued to determine the error checking results (CRC-ERROR bit) on the SDO pin.

If there is a CRC error, the CRC-ALM bit of the status register is set to 1. The FAULT pin can be configured to monitor a CRC error by setting the CRCALM-EN bit.

Table 8-5 Write Operation Error Checking Cycle
BITFIELDDESCRIPTION
31RWEcho RW from previous access cycle (RW = 0).
30CRC-ERRORReturns a 1 when a CRC error is detected; otherwise, returns a 0.
29-24A[5:0]Echo address from previous access cycle.
23-8DO[15:0]Echo data from previous access cycle.
7-0CRCCalculated CRC value of bits 31:8.

A read operation must be followed by a second access cycle to get the requested data on the SDO pin. The error check result (CRC-ERROR bit) from the read command is output on the SDO pin.

As in the case of a write operation failing the CRC check, the CRC-ALM bit of the status register is set to 1, and the ALMOUT pin, if configured for CRC alerts, is set low.

Table 8-6 Read Operation Error Checking Cycle
BITFIELDDESCRIPTION
31RWEcho RW from previous access cycle (RW = 1).
30CRC-ERRORReturns a 1 when a CRC error is detected; otherwise, returns a 0.
29-24A[5:0]Echo address from previous access cycle.
23-8DO[15:0]Readback data requested on previous access cycle.
7-0CRCCalculated CRC value of bits 31:8.
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