ZHCSLS4B August   2020  – July 2021 AMC3302

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagram
    12. 6.12 Insulation Characteristics Curves
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Data Isolation Channel Signal Transmission
      3. 7.3.3 Analog Output
      4. 7.3.4 Isolated DC/DC Converter
      5. 7.3.5 Diagnostic Output
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Shunt Resistor Sizing
        2. 8.2.2.2 Input Filter Design
        3. 8.2.2.3 Differential to Single-Ended Output Conversion
      3. 8.2.3 Application Curve
    3. 8.3 What to Do and What Not to Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

6.9 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C, VDD = 3.0 V to 5.5 V, INP = –50 mV to +50 mV, INN = HGND = 0 V, and the external components listed in the Typical Application section; typical specifications are at TA = 25°C, and VDD = 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
RIN Single-ended input resistance INN = HGND 4.75 kΩ
RIND Differential input resistance 4.9
IIB Input bias current INP = INN = HGND; IIB = (IIBP + IIBN) / 2 –48.5 –36 –28.5 µA
IIO Input offset current IIO = IIBP – IIBN; INP = INN = HGND ±10 nA
CIN Single-ended input capacitance INN = HGND, fIN = 275 kHz 4 pF
CIND Differential input capacitance fIN = 275 kHz 2 pF
ANALOG OUTPUT
Nominal gain 41 V/V
VCMout Common-mode output voltage 1.39 1.44 1.49 V
VCLIPout Clipping differential output voltage VOUT = (VOUTP – VOUTN);
|VIN| = |VINP – VINN| > VClipping 		–2.52 ±2.49 2.52 V
VFailsafe Failsafe differential output voltage VOUT = (VOUTP – VOUTN); VDCDC_OUT ≤ VDCDCUV, or VHLDO_OUT ≤ VHLDOUV –2.63 –2.57 –2.53 V
BW Output bandwidth 290 340 kHz
ROUT Output resistance On OUTP or OUTN 0.2 Ω
Output short-circuit current On OUTP or OUTN, sourcing or sinking, INP = INN = HGND, outputs shorted to either GND or VDD 14 mA
CMTI Common-mode transient immunity |HGND – GND| = 2 kV 95 155 kV/µs
ACCURACY
VOS Input offset voltage(1) (2) TA = 25°C, INP = INN = HGND –50 ±15 50 µV
TCVOS Input offset drift (1) (2) (4) –0.5 ±0.1 0.5 uV/°C
EG Gain error(1) TA = 25°C –0.2% ±0.04% 0.2%
TCEG Gain error drift(1) (5) –35 ±10 35 ppm/°C
Nonlinearity (1) –0.03% ±0.002% 0.03%
SNR Signal-to-noise ratio VIN = 0.1 VPP, fIN = 1 kHz, BW = 10 kHz, 10 kHz filter 77 81 dB
VIN = 0.1 VPP, fIN = 10 kHz,
BW = 100 kHz, 1 MHz filter		 70
THD Total harmonic distortion(3) VIN = 0.1 Vpp, fIN = 10 kHz,
BW = 100 kHz		 –85 dB
Output noise INP = INN = HGND, fIN = 0 Hz,
BW = 100 kHz		 340 µVRMS
CMRR Common-mode rejection ratio fIN = 0 Hz, VCM min ≤ VCM ≤ VCM max –101 dB
fIN = 10 kHz, VCM min ≤ VCM ≤ VCM max –101
PSRR Power-supply rejection ratio VDD from 3.0 V to 5.5 V, at dc, input referred –120 dB
INP = INN = HGND, VDD from 3.0 V to 5.5 V, 10 kHz / 100 mV ripple, input referred –108
POWER SUPPLY
IDD Low-side supply current no external load on HLDO 27.5 40 mA
1 mA  external load on HLDO 29.5 42
VDDUV VDD analog undervoltage detection threshold VDD rising 2.9 V
VDD falling 2.8
VDDPOR VDD digital reset threshold VDD rising 2.5 V
VDD falling 2.4
VDCDC_OUT DCDC output voltage DCDC_OUT to HGND 3.1 3.5 4.65 V
VDCDCUV DCDC output undervoltage detection threshold voltage DCDC output falling 2.1 2.25 V
VHLDO_OUT High-side LDO output voltage HLDO to HGND, up to 1 mA external load 3 3.2 3.4 V
VHLDOUV High-side LDO output undervoltage detection threshold voltage HLDO output falling 2.4 2.6 V
IH High-side supply current for auxiliary circuitry Load connected from HLDO_OUT to HGND, non-switching 1 mA
tAS Analog settling time VDD step to 3.0 V, to OUTP and OUTN valid, 0.1% settling 0.9 1.4 ms
(1) The typical value includes one standard deviation ("sigma") at nominal operating conditions.
(2) This parameter is input referred.
(3) THD is the ratio of the rms sum of the amplitues of first five higher harmonics to the amplitude of the fundamental.
(4) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCVOS = (ValueMAX - ValueMIN) / TempRange
(5) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = (ValueMAX - ValueMIN) / (Value(T=25℃) x TempRange) x 106
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