ZHCSLZ8A September   2020  – August 2021 TPS65988DK

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Requirements and Characteristics
    6. 6.6  Power Consumption Characteristics
    7. 6.7  Power Switch Characteristics
    8. 6.8  Cable Detection Characteristics
    9. 6.9  USB-PD Baseband Signal Requirements and Characteristics
    10. 6.10 Thermal Shutdown Characteristics
    11. 6.11 Oscillator Characteristics
    12. 6.12 I/O Characteristics
    13. 6.13 I2C Requirements and Characteristics
    14. 6.14 SPI Controller Timing Requirements
    15. 6.15 HPD Timing Requirements
    16. 6.16 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB-PD Physical Layer
        1. 8.3.1.1 USB-PD Encoding and Signaling
        2. 8.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 8.3.1.4 USB-PD BMC Transmitter
        5. 8.3.1.5 USB-PD BMC Receiver
      2. 8.3.2  Power Management
        1. 8.3.2.1 Power-On and Supervisory Functions
        2. 8.3.2.2 VBUS LDO
        3. 8.3.2.3 Supply Switch Over
      3. 8.3.3  Port Power Switches
        1. 8.3.3.1 PP_HV Power Switch
          1. 8.3.3.1.1 PP_HV Overcurrent Clamp
          2. 8.3.3.1.2 PP_HV Overcurrent Protection
          3. 8.3.3.1.3 PP_HV OVP and UVP
          4. 8.3.3.1.4 PP_HV Reverse Current Protection
        2. 8.3.3.2 Schottky for Current Surge Protection
        3. 8.3.3.3 PP_EXT Power Path Control
        4. 8.3.3.4 PP_CABLE Power Switch
          1. 8.3.3.4.1 PP_CABLE Overcurrent Protection
          2. 8.3.3.4.2 PP_CABLE Input Good Monitor
        5. 8.3.3.5 VBUS Transition to VSAFE5V
        6. 8.3.3.6 VBUS Transition to VSAFE0V
      4. 8.3.4  Cable Plug and Orientation Detection
        1. 8.3.4.1 Configured as a DFP
        2. 8.3.4.2 Configured as a UFP
        3. 8.3.4.3 Configured as a DRP
        4. 8.3.4.4 Fast Role Swap Signaling
      5. 8.3.5  Dead Battery Operation
        1. 8.3.5.1 Dead Battery Advertisement
        2. 8.3.5.2 BUSPOWER (ADCIN1)
      6. 8.3.6  ADC
      7. 8.3.7  DisplayPort HPD
      8. 8.3.8  Digital Interfaces
        1. 8.3.8.1 General GPIO
        2. 8.3.8.2 I2C
        3. 8.3.8.3 SPI
      9. 8.3.9  Digital Core
      10. 8.3.10 I2C Interfaces
        1. 8.3.10.1 I2C Interface Description
        2. 8.3.10.2 I2C Clock Stretching
        3. 8.3.10.3 I2C Address Setting
        4. 8.3.10.4 Unique Address Interface
        5. 8.3.10.5 I2C Pin Address Setting (ADCIN2)
      11. 8.3.11 SPI Controller Interface
      12. 8.3.12 Thermal Shutdown
      13. 8.3.13 Oscillators
    4. 8.4 Device Functional Modes
      1. 8.4.1 Boot
      2. 8.4.2 Power States
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 USB4 Device Application with Host Charging
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 Power Supply Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 USB Power Delivery Source Capabilities
          2. 9.2.1.2.2 USB Power Delivery Sink Capabilities
          3. 9.2.1.2.3 Supported Data Modes
          4. 9.2.1.2.4 USB4 Hub Controller & PD Controller I2C Communication
          5. 9.2.1.2.5 Dock Management Controller & PD Controller I2C Communication
          6. 9.2.1.2.6 SPI Flash Options
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V Power
      1. 10.1.1 VIN_3V3 Input Switch
      2. 10.1.2 VBUS 3.3-V LDO
    2. 10.2 1.8-V Power
    3. 10.3 Recommended Supply Load Capacitance
  11. 11Layout
    1. 11.1  Layout Guidelines
    2. 11.2  Layout Example
    3. 11.3  Stack-up and Design Rules
    4. 11.4  Main Component Placement
    5. 11.5  Super Speed Type-C Connectors
    6. 11.6  Capacitor Placement
    7. 11.7  CC1/2 Capacitors & ADCIN1/2 Resistors
    8. 11.8  CC and SBU Protection Placement
    9. 11.9  CC Routing
    10. 11.10 DRAIN1 and DRAIN2 Pad Pours
    11. 11.11 VBUS Routing
    12. 11.12 Completed Layout
    13. 11.13 Power Dissipation
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Firmware Warranty Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

GUID-1B998EC6-E3CE-4452-BAC2-7C33D1569F60-low.gifFigure 5-1 RSH Package56-Pin QFNTop View
Table 5-1 Pin Functions
PINTYPE(2)RESET STATE(1)DESCRIPTION
NAMENO.
ADCIN16IInputBoot configuration Input. Connect to resistor divider between LDO_3V3 and GND.
ADCIN210IInputI2C address configuration Input. Connect to resistor divider between LDO_3V3 and GND.
C1_CC124I/OHigh-ZOutput to Type-C CC or VCONN pin for port 1. Filter noise with capacitor to GND.
C1_CC226I/OHigh-ZOutput to Type-C CC or VCONN pin for port 1. Filter noise with capacitor to GND.
C1_USB_N (GPIO19)53I/OInput (High-Z)Port 1 USB D– connection for BC1.2 support.
C1_USB_P (GPIO18)50I/OInput (High-Z)Port 1 USB D+ connection for BC1.2 support.
C2_CC145I/OHigh-ZOutput to Type-C CC or VCONN pin for port 2. Filter noise with capacitor to GND.
C2_CC247I/OHigh-ZOutput to Type-C CC or VCONN pin for port 2. Filter noise with capacitor to GND.
C2_USB_N (GPIO21)55I/OInput (High-Z)Port 2 USB D– connection for BC1.2 support.
C2_USB_P (GPIO20)54I/OInput (High-Z)Port 2 USB D+ connection for BC1.2 support.
DRAIN18, 15, 19, 58——Drain of internal power path 1. Connect thermal pad 58 to as big of pad as possible on PCB for best thermal performance. Short the other pins to this thermal pad.
DRAIN27, 52, 56, 57——Drain of internal power path 2. Connect thermal pad 57 to as big of pad as possible on PCB for best thermal performance. Short the other pins to this thermal pad.
GND 20, 51——Unused pin. Tie to GND.
GPIO016I/OInput (High-Z)General Purpose Digital I/O 0. Float pin when unused. GPIO0 is asserted low during the TPS65988DK boot process. Once device configuration and patches are loaded GPIO0 is released.
GPIO117I/OInput (High-Z)General Purpose Digital I/O 1. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO218I/OInput (High-Z)General Purpose Digital I/O 2. Float pin when unused.
GPIO3 (HPD1)30I/OInput (High-Z)General Purpose Digital I/O 3. Configured as Hot Plug Detect (HPD) TX and RX for port 1 when DisplayPort alternate mode is enabled. Float pin when unused.
GPIO4 (HPD2)31I/OInput (High-Z)General Purpose Digital I/O 4. Configured as Hot Plug Detect (HPD) TX and RX for port 2 when DisplayPort alternate mode is enabled. Float pin when unused.
I2C3_SCL (GPIO5)21I/OInput (High-Z)I2C port 3 serial clock. Open-drain output. Tie pin to I/O voltage through a 10-kΩ resistance when used. Float pin when unused.
I2C3_SDA (GPIO6)22I/OInput (High-Z)I2C port 3 serial data. Open-drain output. Tie pin to I/O voltage through a 10-kΩ resistance when used. Float pin when unused.
I2C3_IRQ (GPIO7)23I/OInput (High-Z)I2C port 3 interrupt detection (port 3 operates as an I2C Master Only). Active low detection. Connect to the I2C slave's interrupt line to detect when the slave issues an interrupt. Float pin when unused.
GPIO1240I/OInput (High-Z)General Purpose Digital I/O 12. Float pin when unused.
GPIO1341I/OInput (High-Z)General Purpose Digital I/O 13. Float pin when unused.
GPIO14 (PWM)42I/OInput (High-Z)General Purpose Digital I/O 14. May also function as a PWM output. Float pin when unused.
GPIO15 (PWM)43I/OInput (High-Z)General Purpose Digital I/O 15. May also function as a PWM output. Float pin when unused.
GPIO16 (PP_EXT1)48I/OInput (High-Z)General Purpose Digital I/O 16. May also function as single wire enable signal for external power path 1. Pull-down with external resistor when used for external path control. Float pin when unused.
GPIO17 (PP_EXT2)49I/OInput (High-Z)General Purpose Digital I/O 17. May also function as single wire enable signal for external power path 2. Pull-down with external resistor when used for external path control. Float pin when unused.
HRESET44I/OInputActive high hardware reset input. Will reinitialize all device settings. Ground pin when HRESET functionality will not be used.
I2C1_IRQ29OHigh-ZI2C port 1 interrupt. Active low. Implement externally as an open drain with a pull-up resistance. Float pin when unused.
I2C1_SCL27I/OHigh-ZI2C port 1 serial clock. Open-drain output. Tie pin to I/O voltage through a 10-kΩ resistance when used or unused.
I2C1_SDA28I/OHigh-ZI2C port 1 serial data. Open-drain output. Tie pin to I/O voltage through a 10-kΩ resistance when used or unused.
I2C2_IRQ34OHigh-ZI2C port 2 interrupt. Active low. Implement externally as an open drain with a pull-up resistance. Float pin when unused.
I2C2_SCL32I/OHigh-ZI2C port 2 serial clock. Open-drain output. Tie pin to I/O voltage through a 10-kΩ resistance when used or unused.
I2C2_SDA33I/OHigh-ZI2C port 2 serial data. Open-drain output. Tie pin to I/O voltage through a 10-kΩ resistance when used or unused.
LDO_1V835PWR—Output of the 1.8-V LDO for internal circuitry. Bypass with capacitor to GND
LDO_3V39PWR—Output of the VBUS to 3.3-V LDO or connected to VIN_3V3 by a switch. Main internal supply rail. Used to power external flash memory. Bypass with capacitor to GND.
PP1_CABLE25PWR—5-V supply input for port 1 C_CC pins. Bypass with capacitor to GND.
PP2_CABLE46PWR—5-V supply input for port 2 C_CC pins. Bypass with capacitor to GND.
PP_HV111, 12PWR—System side of first VBUS power switch. Bypass with capacitor to ground. Tie to ground when unused.
PP_HV21, 2PWR—System side of second VBUS power switch. Bypass with capacitor to ground. Tie to ground when unused.
SPI_CLK38I/OInputSPI serial clock. Ground pin when unused.
SPI_POCI36I/OInputSPI serial controller input from peripheral. Ground pin when unused.
SPI_PICO37I/OInputSPI serial controller output to peripheral. Ground pin when unused.
SPI_CS39I/OInputSPI chip select. Ground pin when unused.
VBUS113, 14PWR—Port side of first VBUS power switch. Bypass with capacitor to ground.
VBUS23, 4PWR—Port side of second VBUS power switch. Bypass with capacitor to ground.
VIN_3V35PWR—Supply for core circuitry and I/O. Bypass with capacitor to GND.
Thermal Pad (PPAD)59GND—Ground reference for the device as well as thermal pad used to conduct heat. from the device. This connection serves two purposes. The first purpose is to provide an electrical ground connection for the device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB. This pad must be connected to a ground plane.
(1) Reset State indicates the state of a given pin immediately following power application, prior to any configuration from firmware.
(2) I = input, O = output, I/O = bidirectional, GND = ground, PWR = power, NC = no connect.
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