After power-up, the internal registers must be
initialized to their default values through a hardware reset
by applying a high pulse on the RESET pin, as shown in Figure 9-4.
Apply AVDD and IOVDD (no
specific sequence required). After AVDD is applied
the internal bandgap reference will power up and
settle out in ~ 2ms.
Configure REFBUF pin (pull
high or low even if configured via SPI later on)
and apply the sampling clock.
Apply hardware reset. After
hardware reset is released, the default registers
are loaded from internal fuses and the internal
power up capacitor calibration is initiated. The
calibration takes approximately 200000 clock
cycles.
Begin programming using SPI
interface.
Figure 9-4 Initialization of Serial Registers after Power
up
Table 9-5 Power-up Timing
MIN
TYP
MAX
UNIT
t1
Power-on delay: delay from power up to logic level of REFBUF pin
2
ms
t2
Delay from REFBUF pin logic level to RESET rising edge