ZHCSM49 April   2021 AMC3336-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Insulation Characteristics Curves
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Modulator
      3. 7.3.3 Isolation Channel Signal Transmission
      4. 7.3.4 Digital Output
        1. 7.3.4.1 Output Behavior in Case of a Full-Scale Input
        2. 7.3.4.2 Output Behavior in Case of a High-Side Supply Failure
      5. 7.3.5 Isolated DC/DC Converter
      6. 7.3.6 Diagnostic Output
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Digital Filter Usage
    2. 8.2 Typical Application
      1. 8.2.1 On-Board Charger Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input Filter Design
          2. 8.2.1.2.2 Bitstream Filtering
        3. 8.2.1.3 Application Curve
      2. 8.2.2 What To Do and What Not To Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Isolation Glossary
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary

6.9 Electrical Characteristics

all minimum and maximum specifications are at TA = –40°C to 125°C, VDD = 3.0 V to 5.5 V, INP = –1 V to +1 V, INN = 0 V, and sinc3 filter with OSR = 256 (unless otherwise noted); typical values are at TA = 25°C, CLKIN = 20 MHz, VDD = 3.3 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
RIN Single-ended input resistance INN = HGND 0.06 1 GΩ
RIND Differential input resistance 0.06 1 GΩ
IIB Input bias current INP = INN = HGND; IIB = (IIBP + IIBN) / 2 –10 10 nA
IIO Input offset current(1) IIO = IIBP – IIBN –5 ±0.5 5 nA
CIN Single-ended input capacitance INN = HGND; fIN = 310 kHz, fCLKIN = 20 MHz 2 pF
CIND Differential input capacitance fIN = 310 kHz, fCLKIN = 20 MHz 2 pF
ACCURACY
EO Offset error(1) INP = INN = HGND, TA = 25°C –0.3 ±0.04 0.3 mV
TCEO Offset error thermal drift(4) –4 4 µV/°C
EG Gain error TA = 25°C –0.2% 0.2%
TCEG Gain error thermal drift(5) –40 40 ppm/°C
DNL Differential nonlinearity Resolution: 16 bits –0.99 0.99 LSB
INL Integral nonlinearity Differential measurement; Resolution: 16 bits –4 4 LSB
Single-ended measurement; Resolution: 16 bits –6 6
SNR Signal-to-noise ratio fIN = 1 kHz 80 84 dB
SINAD Signal-to-noise + distortion fIN = 1 kHz 77 84 dB
THD Total harmonic distortion(3) VIN = 2 VPP, fIN = 1 kHz –93 –80 dB
SFDR Spurious-free dynamic range VIN = 2 VPP, fIN = 1 kHz 79 96 dB
CMRR Common-mode rejection ratio INP = INN, fIN = 0 Hz, VCM min ≤ VCM ≤ VCM max –104 dB
INP = INN, fIN = 10 kHz, –0.5 V ≤ VIN ≤ 0.5 V –89
PSRR Power-supply rejection ratio VDD from 3.0 V to 5.5 V, at dc –109 dB
INP = INN = HGND, VDD from 3.0 V to 5.5 V, 10 kHz / 100 mV ripple –104
DIGITAL I/O
IIN Input leakage current GND ≤ VIN ≤ VDD 7 μA
CIN Input capacitance 4 pF
VIH High-level input voltage 0.7 × VDD VDD + 0.3 V
VIL Low-level input voltage –0.3 0.3 × VDD V
CLOAD Output load capacitance 15 30 pF
VOH High-level output voltage IOH = –20 µA VDD – 0.1 V
IOH = –4 mA VDD – 0.4
VOL Low-level output voltage IOL = 20 µA 0.1 V
IOL = 4 mA 0.4
CMTI Common-mode transient immunity 90 150 kV/μs
POWER SUPPLY
IDD Low-side supply current no external load on HLDO 28.5 42.5 mA
1 mA external load on HLDO 30.5 44.5
VDDUV VDD analog undervoltage detection threshold VDD rising 2.9 V
VDD falling 2.8
VDDPOR VDD digital reset threshold VDD rising 2.5 V
VDD falling 2.4
VDCDC_OUT DC/DC output voltage DCDC_OUT to HGND 3.1 3.5 4.65 V
VDCDCUV DC/DC output undervoltage detection threshold voltage VDCDC_OUT falling 2.1 2.25 V
VHLDO_OUT High-side LDO output voltage HLDO_OUT to HGND,
up to 1 mA external load (2) 		3 3.2 3.4 V
VHLDOUV High-side LDO output undervoltage detection threshold voltage VHLDO_OUT falling 2.4 2.6 V
IH High-side supply current for auxiliary circuitry Load connected from HLDOout to HGND; non-switching; –40℃ ≤ TA ≤ 85℃(2) 1 mA
tSTART Device startup time VDD step from 0 to 3.0 V to bitstrem valid 0.6 1.1 ms
(1) The typical value includes one standard deviation (sigma) at nominal operating condition.
(2) High-side LDO supports full external load (IH) only up to TA = 85℃. See the Isolated DC/DC Converter section for more details.
(3) THD is the ratio of the rms sum of the amplitues of first five higher harmonics to the amplitude of the fundamental.
(4) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCEO = (ValueMAX - ValueMIN) / TempRange
(5) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = (ValueMAX - ValueMIN) / (Value(T=25℃) x TempRange) x 106
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