The control data latch is 371 bits long. The data latch contains dot correction (DC) data, maximum current (MC) data, global brightness control (BC) data, and function control (FC) data. The DC for each constant-current output are controlled by the data in the DC data latch. The control data in the data latch are updated with the lower 371 bits of the common shift register at the LAT rising edge when the common shift register MSB is 1. The 336 bits of DC data are copied from the control data latch when the 65,536th GSCLK is input with RFRESH set to 1 in the control data latch after the GS data are written or the LAT rising edge for GS data writes is input when the RFRESH bit is 0.

When the device is powered up, the data in the control data latch (except the MC bits) are random. Therefore, DC, BC, and FC data must be written to the control data latch before turning on the constant-current outputs. Furthermore, MC data should be set appropriately for the application. Refer to Figure 8-3 for a control data write timing diagram.

Figure 8-3 Control Data Write Timing Diagram for DC, MC, BC, and FC