ZHCSM81A October   2020  – December 2020 TLC6C5748-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Terminal Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Terminal-Equivalent Input and Output Schematic Diagrams
    2. 7.2 Test Circuits
    3. 7.3 Timing Diagrams
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Current Calculation
      2. 8.3.2 Register and Data Latch Configuration
        1. 8.3.2.1 769-Bit Common Shift Register
        2. 8.3.2.2 Grayscale (GS) Data Latch
        3. 8.3.2.3 Control Data Latch
        4. 8.3.2.4 Dot Correction (DC) Data Latch
        5. 8.3.2.5 Maximum Current (MC) Data Latch
        6. 8.3.2.6 Global Brightness Control (BC) Data Latch
        7. 8.3.2.7 Function Control (FC) Data Latch
      3. 8.3.3 Status Information Data (SID)
      4. 8.3.4 LED Open Detection (LOD)
      5. 8.3.5 LED Short Detection (LSD)
      6. 8.3.6 Thermal Shutdown Faults (TSD)
      7. 8.3.7 Noise Reduction
    4. 8.4 Device Functional Modes
      1. 8.4.1 Maximum Current Control (MC) Function
      2. 8.4.2 Dot Correction (DC) Function
      3. 8.4.3 Global Brightness Control (BC) Function
      4. 8.4.4 Grayscale (GS) Function (PWM Control)
        1. 8.4.4.1 Conventional PWM Control
        2. 8.4.4.2 Enhanced Spectrum (ES) PWM Control
        3. 8.4.4.3 Auto Display Repeat Function
        4. 8.4.4.4 Display Timing Reset Function
        5. 8.4.4.5 Auto Data Refresh Function
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Daisy-Chain Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Step-by-Step Design Procedure
          2. 9.2.1.2.2 Maximum Current (MC) Data
          3. 9.2.1.2.3 Global Brightness Control (BC) Data
          4. 9.2.1.2.4 Dot Correction (DC) Data
          5. 9.2.1.2.5 Grayscale (GS) Data
          6. 9.2.1.2.6 Other Control Data
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 静电放电警告
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

8.3.2.7 Function Control (FC) Data Latch

The FC data latch is 5 bits long. This latch enables the auto display repeat and display timing reset functions, and sets the DC data auto refresh, PWM control mode, and the LSD detection voltage. Each function is selected by the data in the control data latch. When the device is powered on, the FC data are random. The FC data bit assignment in the control data latch is shown in Table 8-5.

Table 8-5 Function Control Data Latch Bit Description
BIT
NUMBER		BIT
NAME		DEFAULT VALUE
(Binary)		DESCRIPTION
366DSPRPTN/A
(no default value)		Auto display repeat mode enable bit.
0 = Disabled, 1 = Enabled.
When this bit is 0, the auto display repeat function is disabled. Each constant-current output is turned on and off for one display period.
When this bit is 1, each output repeats the PWM control every 65,536 GSCLKs.
367TMGRSTDisplay timing reset mode enable bit.
0 = Disabled, 1 = Enabled.
When this bit is 0, the GS counter is not reset and the outputs are not forced off even when a LAT rising edge is input for a GS data write.
When this bit is 1, the GS counter is reset to 0 and all outputs are forced off at the LAT rising edge for a GS data write. Afterwards, PWM control resumes from the next GSCLK rising edge.
368RFRESHAuto data refresh mode enable bit.
0 = Disabled, 1 = Enabled.
When this bit is 0, the auto data refresh function is disabled. The data in the common shift register are copied to the GS data latch at the next LAT rising edge for a GS data write. DC data in the control data latch are copied to the DC data latch at the same time.
When this bit is 1, the auto data refresh function is enabled. The data in the common shift register are copied to the GS data latch at the 65,536th GSCLK after the LAT rising edge for a GS data write. DC data in the control data latch are copied to the DC data latch at the same time.
369ESPWMES-PWM mode enable bit.
0 = Disabled, 1 = Enabled.
When this bit is 0, the conventional PWM control mode is selected. If the TLC6C5748-Q1 is used for multiplexing a drive, the conventional PWM mode should be selected to prevent excess on or off switching.
When this bit is 1, ES-PWM control mode is selected.
370LSDVLTLSD detection voltage selection bit.
LED short detection (LSD) detects a fault caused by a shorted LED by comparing the OUTXn voltage to the LSD detection threshold voltage. The threshold voltage is selected by this bit.
When this bit is 0, the LSD voltage is VCC × 70%. When this bit is 1, the LSD voltage is VCC × 90%.
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