ZHCSMA7D January 2022 – April 2024 TPS4811-Q1
PRODUCTION DATA
For limiting inrush current during turn ON of the FET with capacitive loads, use R1, R2, C1 as shown in Figure 8-6. The R1 and C1 components slow down the voltage ramp rate at the gate of the FET. The FET source follows the gate voltage resulting in a controlled voltage ramp across the output capacitors.
Use the Equation 6 to calculate the inrush current during turn-ON of the FET.
Where,
CLOAD is the load capacitance, VBATT is the input voltage and Tcharge is the charge time, V(BST-SRC) is the charge pump voltage (11 V),
Use a damping resistor R2 (~ 10 Ω) in series with C1. Equation 3 can be used to compute required C1 value for a target inrush current. A 100 kΩ resistor for R1 can be a good starting point for calculations.
Connecting PD pin of TPS12000-Q1 directly to the gate of the external FET ensures fast turn OFF without any impact of R1 and C1 components.
C1 results in an additional loading on CBST to charge during turn ON. Use Equation 4 to calculate the required CBST value.
Where, Qg(total) is the total gate charge of the FET.