In some applications, the host does not always monitor charger operation. The INT pin notifies the system host on the device operation. By default, the following events generate an active-low, 256µs INT pulse.

1. Good input source detected
   • V_VBUS < V_{VBUS_OVP} threshold
   • V_VBUS > V_POORSRC (typical 3.4 V) when I_POORSRC (typical 30 mA) current is applied (not a poor source)
2. VBUS_STAT changes state (VBUS_STAT any bit change)
3. Good input source removed
4. Entering IINDPM regulation
5. Entering VINDPM regulation
6. Entering IC junction temperature regulation (TREG)
7. I²C Watchdog timer expired
   • At initial power up, this INT gets asserted to signal I²C is ready for communication
8. Charger status changes state (CHRG_STAT value change), including Charge Complete
9. TS_STAT changes state (TS_STAT any bit change)
10. VBUS over-voltage detected (VBUS_OVP)
11. VAC over-voltage detected (VAC_OVP for VAC1 or VAC2)
12. Junction temperature shutdown (TSHUT)
13. Battery over-voltage detected (BATOVP)
14. System over-voltage detected (VSYS_OVP)
15. IBUS over-current detected (IBUS_OCP)
16. IBAT over-current detected (IBAT_OCP)
17. Charge safety timer expired, including trickle charge and pre-charge and fast charge safety timer expired
18. A rising edge on any of the other *_STAT bits

Each one of these INT sources can be masked off to prevent INT pulses from being sent out when they occur. Three bits exist for each one of these events:

• The STAT bit holds the current status of each INT source
• The FLAG bit holds information on which source produced an INT, regardless of the current status
• The MASK bit is used to prevent the device from sending out INT for each particular event

When one of the above conditions occurs (a rising edge on any of the *_STAT bits), the device sends out an INT pulse and keeps track of which source generated the INT via the FLAG registers. The FLAG register bits are automatically reset to zero after the host reads them, and a new edge on STAT bit is required to re-assert the FLAG. This sequence is illustrated in Figure 9-13.

Figure 9-13 INT Generation Behavior Example