The device provides conversion data for each channel at the data rate. All data are available immediately following DRDY assertion. The conversion status of all channels is available as the DRDY[3:0] bits in the STATUS register. The STATUS register content is automatically output as the response to the NULL command.

Conversion data are 24 bits. The data LSBs are truncated when the device operates with a 16-bit word size. The LSBs are zero padded or the MSBs sign extended when operating with a 32-bit word size depending on the setting of the WLENGTH[1:0] bits in the MODE register.

Data are given in binary two's complement format. Use Equation 8 to calculate the size of one code (LSB).

A positive full-scale input V_IN ≥ +FSR – 1 LSB = 1.2 / Gain – 1 LSB produces an output code of 7FFFFFh and a negative full-scale input (V_IN ≤ –FSR = –1.2 / Gain) produces an output code of 800000h. The output clips at these codes for signals that exceed full-scale.

Table 8-9 summarizes the ideal output codes for different input signals.

Figure 8-19 shows the mapping of the analog input signal to the output codes.

Figure 8-19 Code Transition Diagram