ZHCSMK3B November 2020 – November 2021 ADS131B04-Q1
PRODUCTION DATA
The internal oscillator can be selected as the MCLK source by setting the CLK_SEL bit in the CLOCK register. At device power-up, the internal oscillator is disabled by default.
As shown in Figure 8-3 and Table 8-3, the internal oscillator frequency (fOSC) is scaled using a clock divider to provide the appropriate nominal main clock frequency (fMCLK) for the different power modes. Correspondingly, the modulator clock frequency (fMOD) scales as well because fMOD = fMCLK / 2.
| POWER MODE | CLOCK DIVIDER SETTING | fMCLK | fMOD |
|---|---|---|---|
| HR | 1 | 8.192 MHz | 4.096 MHz |
| LP | 2 | 4.096 MHz | 2.048 MHz |
| VLP | 4 | 2.048 MHz | 1.024 MHz |
To switch between a running CLKIN and the internal oscillator as the MCLK source, put the device in standby mode to avoid creating glitches when switching the clock source because there are no clock sequencers in the device. Likewise, put the device in standby mode before changing power modes because a change in power mode changes the MCLK frequency based on the clock divider setting.
When always using the internal oscillator as the MCLK source, tie the CLKIN pin to DGND. Tying the CLKIN pin to DGND avoids the need to enter standby mode when switching from an external clock to the internal oscillator at power-up or after a reset.