Certain events in the device may require host processor intervention and can be used to trigger interrupts to the host processor. One such event is an audio serial interface (ASI) bus error. The device powers down the record channels if any faults are detected with the ASI bus error clocks, such as:

• Invalid FSYNC frequency
• Invalid SBCLK to FSYNC ratio
• Long pauses of the SBCLK or FSYNC clocks

When an ASI bus clock error is detected, the device shuts down the record channel as quickly as possible. After all ASI bus clock errors are resolved, the device volume ramps back to its previous state to recover the record channel. During an ASI bus clock error, the internal interrupt request (IRQ) interrupt signal asserts low if the clock error interrupt mask register bit INT_MASK0[7] (P0_R51_D7) is set low. The clock fault is also available for readback in the latched fault status register bit INT_LTCH0 (P0_R54), which is a read-only register. Reading the latched fault status register, INT_LTCH0, clears all latched fault status. The device can be additionally configured to route the internal IRQ interrupt signal on the GPIO1 or GPOx pins and also can be configured as open-drain outputs so that these pins can be wire-ANDed to the open-drain interrupt outputs of other devices.

The IRQ interrupt signal can either be configured as active low or active high polarity by setting the INT_POL (P0_R50_D7) register bit. This signal can also be configured as a single pulse or a series of pulses by programming the INT_EVENT[1:0] (P0_R50_D[6:5]) register bits. If the interrupts are configured as a series of pulses, the events trigger the start of pulses that stop when the latched fault status register is read to determine the cause of the interrupt.

The device also supports read-only live-status registers to determine if the channels are powered up or down and if the device is in sleep mode or not. These status registers are located in the DEV_STS0 (P0_R118) and DEV_STS1 (P0_R119) register bits.

The device has a multifunctional GPIO1 pin that can be configured for a desired specific function. Additionally, if the channel is not used for analog input recording, then the analog input pins for that channel (INxP and INxM) can be repurposed as multifunction pins (GPIx and GPOx) by configuring the CHx_INSRC[1:0] register bits located in the CHx_CFG0 register. The maximum number of GPO pins supported by the device is four and the maximum number of GPI pins are four. Table 8-47 lists all possible allocations of these multifunctional pins for the various features.

Each GPOx or GPIOx pin can be independently set for the desired drive configurations setting using the GPOx_DRV[3:0] or GPIO1_DRV[3:0] register bits. Table 8-48 lists the drive configuration settings.

Similarly, the GPO1 pin can be configured using the GPO1_DRV(P0_R34) register bits.

When configured as a general-purpose output (GPO), the GPIO1 or GPOx pin values can be driven by writing the GPIO_VAL or GPOx_VAL (P0_R41) registers. The GPIO_MON (P0_R42) register can be used to readback the status of the GPIO1 pin when configured as a general-purpose input (GPI). Similarly, the GPI_MON (P0_R47) register can be used to readback the status of the GPIx pins when configured as a general-purpose input (GPI).