ZHCSMR7C November   2020  – July 2022 AWR6843AOP

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能方框图
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Pin Functions - Digital and Analog [ALP Package]
    3. 7.3 Pin Attributes
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Power Supply Specifications
    6. 8.6  Power Consumption Summary
    7. 8.7  RF Specification
    8. 8.8  CPU Specifications
    9. 8.9  Thermal Resistance Characteristics for FCBGA Package [ALP0180A]
    10. 8.10 Timing and Switching Characteristics
      1. 8.10.1  Antenna Radiation Patterns
        1. 8.10.1.1 Antenna Radiation Patterns for Receiver
        2. 8.10.1.2 Antenna Radiation Patterns for Transmitter
      2. 8.10.2  Antenna Positions
      3. 8.10.3  Power Supply Sequencing and Reset Timing
      4. 8.10.4  Input Clocks and Oscillators
        1. 8.10.4.1 Clock Specifications
      5. 8.10.5  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.10.5.1 Peripheral Description
        2. 8.10.5.2 MibSPI Transmit and Receive RAM Organization
          1. 8.10.5.2.1 SPI Timing Conditions
          2. 8.10.5.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. 8.10.5.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 8.10.5.3 SPI Peripheral Mode I/O Timings
          1. 8.10.5.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (1) (1)
        4. 8.10.5.4 Typical Interface Protocol Diagram (Peripheral Mode)
      6. 8.10.6  LVDS Interface Configuration
        1. 8.10.6.1 LVDS Interface Timings
      7. 8.10.7  General-Purpose Input/Output
        1. 8.10.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 8.10.8  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 8.10.8.1 Dynamic Characteristics for the CANx TX and RX Pins
      9. 8.10.9  Serial Communication Interface (SCI)
        1. 8.10.9.1 SCI Timing Requirements
      10. 8.10.10 Inter-Integrated Circuit Interface (I2C)
        1. 8.10.10.1 I2C Timing Requirements
      11. 8.10.11 Quad Serial Peripheral Interface (QSPI)
        1. 8.10.11.1 QSPI Timing Conditions
        2. 8.10.11.2 Timing Requirements for QSPI Input (Read) Timings
        3. 8.10.11.3 QSPI Switching Characteristics
      12. 8.10.12 ETM Trace Interface
        1. 8.10.12.1 ETMTRACE Timing Conditions
        2. 8.10.12.2 ETM TRACE Switching Characteristics
      13. 8.10.13 Data Modification Module (DMM)
        1. 8.10.13.1 DMM Timing Requirements
      14. 8.10.14 JTAG Interface
        1. 8.10.14.1 JTAG Timing Conditions
        2. 8.10.14.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 8.10.14.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Processor Subsystem
      3. 9.3.3 Automotive Interface
      4. 9.3.4 Host Interface
      5. 9.3.5 Main Subsystem Cortex-R4F
      6. 9.3.6 DSP Subsystem
      7. 9.3.7 Hardware Accelerator
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Channels (Service) for User Application
        1. 9.4.1.1 GP-ADC Parameter
  10. 10Monitoring and Diagnostics
    1. 10.1 Monitoring and Diagnostic Mechanisms
      1. 10.1.1 Error Signaling Module
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Reference Schematic
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for ALP, 15 × 15 mm

7.2.1 Pin Functions - Digital and Analog [ALP Package]

NAMEI/ODESCRIPTIONNO.
DIGITAL
BSS_UART_TXODebug UART Transmit [Radar Block]D3, E2, K3, L2, U8, U10, U16, V16
CAN1_FD_RXICAN1 FD (MCAN) Receive SignalA4, B3, E2, F2, K2, U8, V16
CAN1_FD_TX O CAN1 FD (MCAN) Transmit Signal C2, C3, D1, D3, J3, T3, U16
CAN2_FD_RX I CAN2 FD (MCAN) Receive Signal D2
CAN2_FD_TX O CAN2 FD (MCAN) Transmit Signal B4
DMM0IDebug Interface (Hardware In Loop) - Data LineU7
DMM1IDebug Interface (Hardware In Loop) - Data LineU6
DMM2IDebug Interface (Hardware In Loop) - Data LineV5
DMM3IDebug Interface (Hardware In Loop) - Data LineU5
DMM4IDebug Interface (Hardware In Loop) - Data LineV3
DMM5IDebug Interface (Hardware In Loop) - Data LineM1
DMM6IDebug Interface (Hardware In Loop) - Data LineL2
DMM7IDebug Interface (Hardware In Loop) - Data LineL1
DMM8IDebug Interface (Hardware In Loop) - Data LineC3
DMM9IDebug Interface (Hardware In Loop) - Data LineB3
DMM10IDebug Interface (Hardware In Loop) - Data LineC4
DMM11IDebug Interface (Hardware In Loop) - Data LineA3
DMM12IDebug Interface (Hardware In Loop) - Data LineB4
DMM13IDebug Interface (Hardware In Loop) - Data LineA4
DMM14IDebug Interface (Hardware In Loop) - Data LineC5
DMM15IDebug Interface (Hardware In Loop) - Data LineB5
DMM_CLKIDebug Interface (Hardware In Loop) - ClockU3
DMM_MUX_INIDebug Interface (Hardware In Loop) Mux Select between DMM1 and DMM2 (Two Instances)L3, M3, U12
DMM_SYNCIDebug Interface (Hardware In Loop) - SyncU4
DSS_UART_TXODebug UART Transmit [DSP]D2, F2, G3, H2, L1
EPWM1AOPWM Module 1 - Output AB4, U16, V13
EPWM1BOPWM Module 1 - Output BA4, M2, U16, V10
EPWM1SYNCIIPWM Module 1 - Sync InputC3, L3
EPWM1SYNCOIPWM Module 1 - Sync OutputB3
EPWM2AOPWM Module 2- Output AC5, M2, U16, V10, V16
EPWM2BOPWM Module 2 - Output BB5, V16
EPWM2SYNCOOPWM Module 2 - Sync OutputV3
EPWM3AOPWM Module 3 - Output AC4, V16
EPWM3BOPWM Module 3 - Output AA3
EPWM3SYNCOOPWM Module 3 - Sync OutputU5
GPIO_0IOGeneral-purpose I/OM2
GPIO_1IOGeneral-purpose I/OL3
GPIO_2IOGeneral-purpose I/OK3
GPIO_3IOGeneral-purpose I/OD2
GPIO_4IOGeneral-purpose I/OD3
GPIO_5IOGeneral-purpose I/OE2
GPIO_6IOGeneral-purpose I/OJ2
GPIO_7IOGeneral-purpose I/OH2
GPIO_8IOGeneral-purpose I/OH3
GPIO_9IOGeneral-purpose I/OG2
GPIO_10IOGeneral-purpose I/OJ3
GPIO_11IOGeneral-purpose I/OK2
GPIO_12IOGeneral-purpose I/OB2
GPIO_13IOGeneral-purpose I/OM2
GPIO_14IOGeneral-purpose I/OU16
GPIO_15IOGeneral-purpose I/OV16
GPIO_16IOGeneral-purpose I/OL3
GPIO_17IOGeneral-purpose I/OT3
GPIO_18IOGeneral-purpose I/OU8
GPIO_19IOGeneral-purpose I/OF2
GPIO_20IOGeneral-purpose I/OD1
GPIO_21IOGeneral-purpose I/OG1
GPIO_22IOGeneral-purpose I/OG3
GPIO_23IOGeneral-purpose I/OU9
GPIO_24IOGeneral-purpose I/OU10
GPIO_25IOGeneral-purpose I/OV13
GPIO_26IOGeneral-purpose I/OK3
GPIO_27IOGeneral-purpose I/OV10
GPIO_28IOGeneral-purpose I/OU12
GPIO_29IOGeneral-purpose I/OM3
GPIO_30IOGeneral-purpose I/OC2, D2
GPIO_31IOGeneral-purpose I/OU7
GPIO_32IOGeneral-purpose I/OU6
GPIO_33IOGeneral-purpose I/OV5
GPIO_34IOGeneral-purpose I/OU5
GPIO_35IOGeneral-purpose I/OV3
GPIO_36IOGeneral-purpose I/OM1
GPIO_37IOGeneral-purpose I/OL2
GPIO_38IOGeneral-purpose I/OL1
GPIO_39IOGeneral-purpose I/OC3
GPIO_40IOGeneral-purpose I/OB3
GPIO_41IOGeneral-purpose I/OC4
GPIO_42IOGeneral-purpose I/OA3
GPIO_43IOGeneral-purpose I/OB4
GPIO_44IOGeneral-purpose I/OA4
GPIO_45IOGeneral-purpose I/OC5
GPIO_46IOGeneral-purpose I/OB5
GPIO_47IOGeneral-purpose I/OU3
I2C_SCLIOI2C ClockG3, V16
I2C_SDAIOI2C DataG1, U16
LVDS_TXP[0]ODifferential data Out – Lane 0N2
LVDS_TXM[0]ODifferential data Out – Lane 0N1
LVDS_TXP[1]ODifferential data Out – Lane 1P2
LVDS_TXM[1]ODifferential data Out – Lane 1P1
LVDS_CLKPODifferential clock OutR1
LVDS_CLKMODifferential clock OutR2
LVDS_FRCLKPODifferential Frame ClockT1
LVDS_FRCLKMODifferential Frame ClockT2
MCU_CLKOUTOProgrammable clock given out to external MCU or the processorV13
MSS_UARTA_RXIMain Subsystem - UART A ReceiveE2, U9, V16
MSS_UARTA_TXOMain Subsystem - UART A TransmitD3, U7, U10, U16
MSS_UARTB_RXIOMain Subsystem - UART B ReceiveU12, V16
MSS_UARTB_TXOMain Subsystem - UART B TransmitD3, E2, K3, M1, T3, U10, U16
NDMM_ENIDebug Interface (Hardware In Loop) Enable - Active Low SignalU10, U16
NERROR_INIFailsafe input to the device. Nerror output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by FirmwareU14
NERROR_OUTOOpen drain fail safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset.U15
PMIC_CLKOUTOOutput Clock from AWR6843AOP device for PMICK3, M2, V10
QSPI[0]IOQSPI Data Line #0 (Used with Serial Data Flash)H3
QSPI[1]IQSPI Data Line #1 (Used with Serial Data Flash)G2
QSPI[2]IQSPI Data Line #2 (Used with Serial Data Flash)J3
QSPI[3]IQSPI Data Line #3 (Used with Serial Data Flash)K2
QSPI_CLKOQSPI Clock (Used with Serial Data Flash)H2
QSPI_CLK_EXTIQSPI Clock (Used with Serial Data Flash)D3
QSPI_CS_NOQSPI Chip Select (Used with Serial Data Flash)J2
RS232_RXIDebug UART (Operates as Bus Master) - Receive SignalV16
RS232_TXODebug UART (Operates as Bus Master) - Transmit SignalU16
SOP[0]ISense On Power - Line#0U10
SOP[1]ISense On Power - Line#1M3
SOP[2]ISense On Power - Line#2V10
SPIA_CLKIOSPI Channel A - ClockD2
SPIA_CS_NIOSPI Channel A - Chip SelectC2
SPIA_MISOIOSPI Channel A - Master In Slave OutD1
SPIA_MOSIIOSPI Channel A - Master Out Slave InF2
SPIB_CLKIOSPI Channel B - ClockE2, H2
SPIB_CS_NIOSPI Channel B Chip Select (Instance ID 0)D3, J2
SPIB_CS_N_1IOSPI Channel B Chip Select (Instance ID 1)B2, L3, M3
SPIB_CS_N_2IOSPI Channel B Chip Select (Instance ID 2)G2, L3, M3
SPIB_MISOIOSPI Channel B - Master In Slave OutG3, H3
SPIB_MOSIIOSPI Channel B - Master Out Slave InG1, G2
SPI_HOST_INTROOut of Band Interrupt to an external host communicating over SPIB2
SYNC_INILow frequency Synchronization signal inputU12
SYNC_OUTOLow Frequency Synchronization Signal outputK3, L3, M3, U12
TCKIJTAG Test ClockT3
TDIIJTAG Test Data InputU9
TDOOJTAG Test Data OutputU10
TMSIJTAG Test Mode SignalU8
TRACE_CLKODebug Trace Output - ClockU3
TRACE_CTLODebug Trace Output - ControlU4
TRACE_DATA_0ODebug Trace Output - Data LineU7
TRACE_DATA_1ODebug Trace Output - Data LineU6
TRACE_DATA_2ODebug Trace Output - Data LineV5
TRACE_DATA_3ODebug Trace Output - Data LineU5
TRACE_DATA_4ODebug Trace Output - Data LineV3
TRACE_DATA_5ODebug Trace Output - Data LineM1
TRACE_DATA_6ODebug Trace Output - Data LineL2
TRACE_DATA_7ODebug Trace Output - Data LineL1
TRACE_DATA_8ODebug Trace Output - Data LineC3
TRACE_DATA_9ODebug Trace Output - Data LineB3
TRACE_DATA_10ODebug Trace Output - Data LineC4
TRACE_DATA_11ODebug Trace Output - Data LineA3
TRACE_DATA_12ODebug Trace Output - Data LineB4
TRACE_DATA_13ODebug Trace Output - Data LineA4
TRACE_DATA_14ODebug Trace Output - Data LineC5
TRACE_DATA_15ODebug Trace Output - Data LineB5
FRAME_STARTOPulse signal indicating the start of each frameK3, V10, V13
CHIRP_STARTOPulse signal indicating the start of each chirpK3, V10, V13
CHIRP_ENDOPulse signal indicating the end of each chirpK3, V10, V13
ADC_VALIDOWhen high, indicating valid ADC samplesB2, L3, M2
WARM_RESETIOOpen drain fail safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset.U13
ANALOG
NRESETIPower on reset for chip. Active lowU11
CLKPIIn XTAL mode: Differential port for reference crystal In External clock mode: Single ended input reference clock portA7
CLKMIIn XTAL mode: Differential port for reference crystal In External clock mode: Connect this port to groundB7
OSC_CLKOUTOReference clock output from clocking sub system after cleanup PLL (1.4-V output voltage swing).A14, K3
VBGAPODevice's Band Gap Reference OutputA16
VDDINPower1.2V digital power supplyE1, J1, V4, V8, V15
VIN_SRAMPower1.2V power rail for internal SRAMA5, V6, V12
VNWAPower1.2V power rail for SRAM array back biasC1, V7, V14
VIOINPowerI/O Supply (3.3V or 1.8V): All CMOS I/Os would operate on this supplyH1, V9
VIOIN_18Power1.8V supply for CMOS IOB1, F1, K1, V11
VIN_18CLKPower1.8V supply for clock moduleC15, C18
VIOIN_18DIFFPower1.8V supply for LVDS portU2
VPPPowerVoltage supply for fuse chainV2
VIN_13RF1Power1.3V Analog and RF supply,VIN_13RF1 and VIN_13RF2 could be shorted on the boardJ16, J17, J18
VIN_13RF2Power1.3V Analog and RF supplyH16, H17, H18
VIN_18BBPower1.8V Analog base band power supplyM16, M17, M18
VIN_18VCOPower1.8V RF VCO supplyA12, C11
VSSGroundDigital groundA1, A2, E3, F3, N3, P3, R3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, U1, V1
VSSAGroundAnalog groundA6, A8, A11, A13, A15, A17, A18, B6, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, C6, C7, C8, C12, C13, C14, C16, C17, D16, D17, D18, E16, E17, E18, F16, F17, F18, K16, K17, K18, L16, L17, L18, N16, N17, N18, P16, R16, R17, T17, U17, U18, V17, V18
VOUT_14APLLOInternal LDO outputA10
VOUT_14SYNTHOInternal LDO outputA9
VOUT_PAIOInternal LDO outputG16, G17, G18
Analog Test1 / GPADC1IOAnalog IO dedicated for ADC serviceP18
Analog Test2 / GPADC2IOAnalog IO dedicated for ADC serviceP17
Analog Test3 / GPADC3IOAnalog IO dedicated for ADC serviceR18
Analog Test4 / GPADC4IOAnalog IO dedicated for ADC serviceT18
ANAMUX / GPADC5IOAnalog IO dedicated for ADC serviceC9
VSENSE / GPADC6IOAnalog IO dedicated for ADC serviceC10
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