ZHCSMZ3A December   2020  – June 2021 PCM1820 , PCM1821

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 7.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hardware Control
      2. 8.3.2 Audio Serial Interfaces
        1. 8.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 8.3.2.2 Inter IC Sound (I2S) Interface
      3. 8.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 8.3.4 Input Channel Configurations
      5. 8.3.5 Reference Voltage
      6. 8.3.6 Signal-Chain Processing
        1. 8.3.6.1 Digital High-Pass Filter
        2. 8.3.6.2 Configurable Digital Decimation Filters
          1. 8.3.6.2.1 Linear Phase Filters
            1. 8.3.6.2.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 8.3.6.2.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 8.3.6.2.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 8.3.6.2.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 8.3.6.2.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 8.3.6.2.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 8.3.6.2.1.7 Sampling Rate: 192 kHz or 176.4 kHz
          2. 8.3.6.2.2 Low-Latency Filters
            1. 8.3.6.2.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.6.2.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.6.2.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.6.2.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.6.2.2.5 Sampling Rate: 96 kHz or 88.2 kHz
      7. 8.3.7 Dynamic Range Enhancer (DRE)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

8.3.2 Audio Serial Interfaces

Digital audio data flows between the host processor and the PCM182x on the digital audio serial interface (ASI), or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for the I2S, and the pin-selectable master-slave configurability for bus clock lines.

The device supports an audio bus master or slave mode of operation using the hardware pin MSZ. In slave mode, FSYNC and BCLK work as input pins whereas in master mode, FSYNC and BCLK work as output pins generated by the device. Table 8-1 shows the master and slave mode selection using the MSZ pin.

Table 8-1 Master and Slave Mode Selection
MSZ MASTER AND SLAVE SELECTION
Low Slave mode of operation
High Master ode of operation

The bus protocol TDM or I2S format can be selected by using the FMT0 pin. As shown in Table 8-2, these modes are all most significant byte (MSB)-first, pulse code modulation (PCM) data format, with an output channel data word-length of 32 bits.

Table 8-2 Audio Serial Interface Format
FMT0 AUDIO SERIAL INTERFACE FORMAT
Low 2-channel output with inter IC sound (I2S) mode
High 2-channel output with time division multiplexing (TDM) mode
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |