ZHCSMZ6B December   2020  – July 2022 ADC3664

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Analog Input Termination and DC Bias
            1. 8.3.1.2.2.1 AC-Coupling
            2. 8.3.1.2.2.2 DC-Coupling
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
        3. 8.3.4.3 FS/4 Mixing with Real Output
        4. 8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 8.3.4.5 Decimation Filter
        6. 8.3.4.6 SYNC
        7. 8.3.4.7 Output Formatting with Decimation
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Output Formatter
        2. 8.3.5.2 Output Bit Mapper
        3. 8.3.5.3 Output Interface/Mode Configuration
          1. 8.3.5.3.1 Configuration Example
        4. 8.3.5.4 Output Data Format
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

6.8 Timing Requirements

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 105°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ADC Timing Specifications
tAD Aperture Delay 0.85 ns
tA Aperture Jitter square wave clock with fast edges 250 fs
tJ Jitter on DCLKIN ± 50 ps pk-pk
Recory time from +6 dB overload condition SNR within 1 dB of expected value 1 Clock cycle
tACQ Signal acquisition period referenced to sampling clock falling edge -TS/4 Sampling clock period
tCONV Signal conversion period 6 ns
Wake up time Time to valid data after coming out of power down. Internal reference. Bandgap reference enabled, single ended clock 13 us
Bandgap reference enabled, differential clock 15
Bandgap reference disabled, single ended clock 2.4 ms
Bandgap reference disabled, differential clock 2.3
Time to valid data after coming out of power down.
External 1.6V reference.		 Bandgap reference enabled, single ended clock 13 us
Bandgap reference enabled, differential clock 14
Bandgap reference disabled, single ended clock 2.0 ms
Bandgap reference disabled, differential clock 2.2
tS,SYNC Setup time for SYNC input signal Referenced to sampling clock rising edge 500 ps
tH,SYNC Hold time for SYNC input signal 600
ADC Latency Signal input to data output 1/2-wire SLVDS 1 Clock cycles
1-wire SLVDS 1
2-wire SLVDS 2
Add. Latency Real decimation by 2 21   Output clock cycles
Complex decimation by 2     22  
Real or complex decimation by 4, 8, 16, 32     23  
Interface Timing: Serial LVDS Interface
tPD Propagation delay: sampling clock falling edge to DCLK rising edge Delay between sampling clock falling edge to DCLKIN falling edge < 2.5ns.
TDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN falling edge		 2 +
TDCLK +
tCDCLK		 3 +
TDCLK +
tCDCLK		 4 +
TDCLK +
tCDCLK		 ns
Delay between sampling clock falling edge to DCLKIN falling edge >= 2.5ns.
TDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN falling edge		 2 +
tCDCLK		 3 +
tCDCLK		 4 +
tCDCLK
tCD DCLK rising edge to output data delay,
2-wire SLVDS, 14-bit		 Fout = 65 MSPS, DA/B0,1 = 455 MBPS 0 0.1 ns
Fout = 80 MSPS, DA/B0,1 = 560 MBPS 0 0.1
Fout = 125 MSPS, DA/B0,1 = 875 MBPS -0.2 0.1
DCLK rising edge to output data delay,
1-wire SLVDS, 14-bit		 Fout = 65 MSPS, DA/B0 = 910 MBPS 0 0.1
DCLK rising edge to output data delay,
1-wire SLVDS, 16-bit		 Fout = 10 MSPS, DA/B0 = 160 MBPS 0 0.1
Fout = 25 MSPS, DA/B0 = 400 MBPS 0 0.1
Fout = 62.5 MSPS, DA/B0= 1000 MBPS -0.6 0.1
DCLK rising edge to output data delay,
1/2-wire SLVDS, 16-bit		 Fout = 5 MSPS, DA0 = 160 MBPS 0 0.1
Fout = 10 MSPS, DA0 = 320 MBPS 0 0.1
Fout = 25 MSPS, DA0 = 800 MBPS 0 0.1
tDV Data valid, 2-wire SLVDS, 14-bit Fout = 65 MSPS, DA/B0,1 = 455 MBPS 1.8 1.9 ns
Fout = 80 MSPS, DA/B0,1 = 560 MBPS 1.4 1.5
Fout = 125 MSPS, DA/B0,1 = 875 MBPS 0.6 0.8
Data valid, 1-wire SLVDS, 14-bit Fout = 65 MSPS, DA/B0 = 910 MBPS 0.6 0.8
Data valid, 1-wire SLVDS, 16-bit Fout = 10 MSPS, DA/B0 = 160 MBPS 5.7 5.8
Fout = 25 MSPS, DA/B0 = 400 MBPS 2.0 2.1
Fout = 62.5 MSPS, DA/B0= 1000 MBPS 0.5 0.6
Data valid, 1/2-wire SLVDS, 16-bit Fout = 5 MSPS, DA0 = 160 MBPS 5.7 5.8
Fout = 10 MSPS, DA0 = 320 MBPS 2.7 2.8
Fout = 25 MSPS, DA0 = 800 MBPS 0.8 0.9
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input
fCLK,SCLK Serial clock frequency 20 MHz
tS,SEN SEN falling edge to SCLK rising edge 10 ns
tH,SEN SCLK rising edge to SEN rising edge 9
tS,SDIO SDIO setup time from rising edge of SCLK 17
tH,SDIO SDIO hold time from rising edge of SCLK 9
SERIAL PROGRAMMING INTERFACE (SDIO) - Output
tOZD Delay from falling edge of 16th SCLK cycle during read operation for SDIO transition from tri-state to valid data 3.9 10.8 ns
tODZ Delay from SEN rising edge for SDIO transition from valid data to tri-state 3.4 14
tOD Delay from falling edge of 16th SCLK cycle during read operation to SDIO valid 3.9 10.8
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