ZHCSN12B December   2020  – October 2022 ADC3681 , ADC3682 , ADC3683

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements
    9. 6.9  Typical Characteristics - ADC3681
    10. 6.10 Typical Characteristics - ADC3682
    11. 6.11 Typical Characteristics - ADC3683
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Analog Input Termination and DC Bias
            1. 8.3.1.2.2.1 AC-Coupling
            2. 8.3.1.2.2.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
        3. 8.3.4.3 FS/4 Mixing with Real Output
        4. 8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 8.3.4.5 Decimation Filter
        6. 8.3.4.6 SYNC
        7. 8.3.4.7 Output Formatting with Decimation
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Output Formatter
        2. 8.3.5.2 Output Scrambler
        3. 8.3.5.3 Output Bit Mapper
        4. 8.3.5.4 Output Interface/Mode Configuration
          1. 8.3.5.4.1 Configuration Example
        5. 8.3.5.5 Output Data Format
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Power Down Options
      3. 8.4.3 Digital Channel Averaging
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Map
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

6.11 Typical Characteristics - ADC3683

Typical values at TA = 25 °C, ADC sampling rate = 65 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD = 1.8 V, external 1.6 V voltage reference, unless otherwise noted.

SNR = 84.2 dBFS, SFDR = 81 dBc, Non HD23 = 101 dBFS
Figure 6-40 Single Tone FFT at FIN = 1 MHz
SNR = 84.8 dBFS, SFDR = 81 dBc, Non HD23 = 103 dBFS
Figure 6-42 Single Tone FFT at FIN = 5 MHz, AIN = -20 dBFS
SNR = 81.1 dBFS, SFDR = 84 dBc, Non HD23 = 95 dBFS
Figure 6-44 Single Tone FFT at FIN = 40 MHz
SNR = 75.1 dBFS, SFDR = 75 dBc, Non HD23 = 93 dBFS
Figure 6-46 Single Tone FFT at FIN = 100 MHz
AIN = -20 dBFS/tone, IMD3 = 95 dBc
Figure 6-48 Two Tone FFT at FIN = 10/12 MHz
Figure 6-50 AC Performance vs Input Frequency
FIN = 5 MHz
Figure 6-52 AC Performance vs Input Amplitude
Figure 6-54 AC Performance vs Clock Amplitude
FIN = 5 MHz
Figure 6-56 AC Performance vs AVDD
FIN = 5 MHz
Figure 6-58 AC Performance vs Clock Duty Cycle
FIN = 5 MHz
Figure 6-60 INL vs Code
Figure 6-62 DC Offset Histogram
FIN = 5 MHz, DDC Bypass
Figure 6-64 Current vs Sampling Rate
FIN = 5 MHz, Complex Decimation by 32
Figure 6-66 IIOVDD Current vs Output Interface
SNR = 83.8 dBFS, SFDR = 89 dBc, Non HD23 = 99 dBFS
Figure 6-41 Single Tone FFT at FIN = 5 MHz
SNR = 83.8 dBFS, SFDR = 92 dBc, Non HD23 = 98 dBFS
Figure 6-43 Single Tone FFT at FIN = 10 MHz
SNR = 77.3 dBFS, SFDR = 86 dBc, Non HD23 = 92 dBFS
Figure 6-45 Single Tone FFT at FIN = 64 MHz
AIN = -7 dBFS/tone, IMD3 = 88 dBc
Figure 6-47 Two Tone FFT at FIN = 10/12 MHz
AIN = -7 dBFS/tone, IMD3 = 83 dBc
Figure 6-49 Two Tone FFT at FIN = 40/45 MHz
Figure 6-51 ENOB vs Input Frequency
FIN = 5 MHz
Figure 6-53 AC Performance vs Sampling Rate
Single ended clock input
Figure 6-55 AC Performance vs Clock Amplitude
FIN = 5 MHz
Figure 6-57 AC Performance vs VCM vs Temperature
Figure 6-59 Isolation vs Input Frequency
FIN = 5 MHz
Figure 6-61 DNL vs Code
FIN = 1 MHz
Figure 6-63 Pulse Response
FIN = 5 MHz, 2-wire
Figure 6-65 IIOVDD Current vs Decimation
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