ZHCSN12B December 2020 – October 2022 ADC3681 , ADC3682 , ADC3683
PRODUCTION DATA
The device includes an optional output scrambler feature. Scrambling is performed on each serial output lane independently. When enabled, the serial output bit stream is scrambled where each output bit is XOR-ed with 2 previous bits (k-14 and k-15) as shown in Figure 8-42. For descrambling, note that the output bit mapper is located after the scrambler.
On the external receiver, the incoming serial data stream can be descrambled by XOR-ing each incoming bit with 2 previous bits (k-14 and k-15).
Scrambling is enabled by disabling digital bypass (register 0x24, D2) and enabling scrambling (register 0x22, D6).