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ZHCSN12B December 2020 – October 2022 ADC3681 , ADC3682 , ADC3683

PRODUCTION DATA

9.2 Initialization Set Up

After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin, as shown in Figure 9-6.

Apply AVDD and IOVDD (no specific sequence required). After AVDD is applied the internal bandgap reference will power up and settle out in ~ 2ms.
Configure REFBUF pin (pull high or low even if configured via SPI later on) and apply the sampling clock.
Apply hardware reset. After hardware reset is released, the default registers are loaded from internal fuses and the internal power up capacitor calibration is initiated. The calibration takes approximately 200000 clock cycles.
Begin programming using SPI interface.

Figure 9-6 Initialization of serial registers after power up

Table 9-5 Power-up timing

		MIN	UNIT
t₁	Power-on delay: delay from power up to logic level of REFBUF pin	2	ms
t₂	Delay from REFBUF pin logic level to RESET rising edge	100	ns
t₃	RESET pulse width	1	us
t₄	Delay from RESET disable to SEN active	~ 200000	clock cycles