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ZHCSN42A August 2021 – May 2022 ADC08DJ5200RF

PRODUCTION DATA

6.9 Timing Requirements

typical values at T_A = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN = 347 MHz, A_IN = –1 dBFS, f_CLK = 5.2 GHz, filtered 1-V_PP sine-wave clock, JMODE = 6, Dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table

			MIN	NOM	MAX	UNIT
DEVICE (SAMPLING) CLOCK (CLK+, CLK–)
f_CLK	Input clock frequency (CLK±), both single-channel and dual-channel modes⁽¹⁾		800		5200	MHz
t_CLK	Input clock period (CLK±), both single-channel and dual-channel modes⁽¹⁾		192		1250	ps
SYSREF (SYSREF+, SYSREF–)
t_INV(SYSREF)	Width of invalid SYSREF capture region of CLK± period, indicating setup or hold time violation, as measured by SYSREF_POS status register, SYSREF_ZOOM = 1⁽²⁾			48		ps
t_INV(TEMP)	Drift of invalid SYSREF capture region over temperature, positive number indicates a shift toward MSB of SYSREF_POS register, SYSREF_ZOOM = 1			0.02		ps/°C
t_INV(VA11)	Drift of invalid SYSREF capture region over VA11 supply voltage, positive number indicates a shift toward MSB of SYSREF_POS register, SYSREF_ZOOM = 1			-0.03		ps/mV
t_STEP(SP)	Delay of SYSREF_POS LSB⁽³⁾	SYSREF_ZOOM = 0		39		ps
t_STEP(SP)	Delay of SYSREF_POS LSB⁽³⁾	SYSREF_ZOOM = 1		24		ps
t_{(PH_SYS)}	Minimum SYSREF± assertion duration with SYSREF Windowing after SYSREF± rising edge event			5*T_CLK +4.5		ns
t_{(PL_SYS)}	Minimum SYSREF± de-assertion duration with SYSREF Windowing after SYSREF± falling edge event			5*T_CLK +4.5		ns
JESD204B SYNC TIMING (SYNCSE OR TMSTP±)
t_(SYNCSE)	SYNCSE minimum assertion time to trigger link resynchronization			4		Frames
SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS)
f_CLK(SCLK)	Serial clock frequency				15.625	MHz
t_(PH)	Serial clock high value pulse duration		32			ns
t_(PL)	Serial clock low value pulse duration		32			ns
t_SU(SCS)	Setup time from SCS to rising edge of SCLK		30			ns
t_H(SCS)	Hold time from rising edge of SCLK to SCS		30			ns
t_SU(SDI)	Setup time from SDI to rising edge of SCLK		25			ns
t_H(SDI)	Hold time from rising edge of SCLK to SDI		3			ns

(1) Unless functionally limited to a smaller range in the Operating Modes table based on programmed JMODE.

(2) Use SYSREF_POS to select an optimal SYSREF_SEL value for the SYSREF capture, see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section for more information on SYSREF windowing. The invalid region, specified by t_INV(SYSREF), indicates the portion of the CLK± period(t_CLK), as measured by SYSREF_SEL, that may result in a setup and hold violation. Verify that the timing skew between SYSREF± and CLK± over system operating conditions from the nominal conditions (that used to find optimal SYSREF_SEL) does not result in the invalid region occurring at the selected SYSREF_SEL position in SYSREF_POS, otherwise a temperature dependent SYSREF_SEL selection may be needed to track the skew between CLK± and SYSREF±.

(3) It is recommended to use SYSREF_ZOOM = 0 below f_CLK = 3GHz and SYSREF_ZOOM = 1 above f_CLK = 3GHz