米6体育平台手机版

ZHCSNB6A April 2021 – February 2022 TPS23882B

PRODUCTION DATA

7.5 Electrical Characteristics

Conditions are –40 < T_J < 125 °C unless otherwise noted.V_VDD = 3.3 V,V_VPWR = 54 V, V_DGND = V_AGND,DGND, KSENSA, KSENSB, KSENSC and KSENSD connected to AGND, and all outputs are unloaded, 2xFBn =0. Positive currents are into pins. R_S = 0.200 Ω, to KSENSA (SEN1 orSEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or SEN6) or to KSENSD (SEN7 or SEN8). Typical values are at 25 °C. All voltages are with respect to AGND unless otherwise noted. Operating registers loaded with default values unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT SUPPLY VPWR
I_VPWR	VPWR Current consumption	VVPWR = 54 V		10	12.5	mA
V_{UVLOPW_F}	VPWR UVLO falling threshold	Check internal oscillator stops operating	14.5		17.5	V
V_{UVLOPW_R}	VPWR UVLO rising threshold		15.5		18.5	V
V_{PUV_F}	VPWR Undervoltage falling threshold	VPUV threshold	25	26.5	28	V
INPUT SUPPLY VDD
I_VDD	VDD Current consumption			6	12	mA
V_{UVDD_F}	VDD UVLO falling threshold	For channel deassertion	2.1	2.25	2.4	V
V_{UVDD_R}	VDD UVLO rising threshold		2.45	2.6	2.75	V
V_{UVDD_HYS}	Hysteresis VDD UVLO			0.35		V
V_{UVW_F}	VDD UVLO warning threshold	VDD falling	2.6	2.8	3	V
A/D CONVERTERS
T_{CONV_I}	Conversion time	All ranges, each channel	0.64	0.8	0.96	ms
T_{CONV_V}	Conversiontime	All ranges, each channel	0.82	1.03	1.2	ms
T_{INT_CUR}	Integration time, Current	Each channel, channel ON current	82	102	122	ms
T_{INT_DET}	Integration time, Detection		13.1	16.6	20	ms
T_{INT_channelV}	Integration time, Channel Voltage	channel powered	3.25	4.12	4.9	ms
T_{INT_inV}	Integration time, Input Voltage		3.25	4.12	4.9	ms
	Input voltage conversion scale factor and accuracy	VVPWR = 57 V	15175	15565	15955	Counts
		VVPWR = 57 V	55.57	57	58.43	V
		VVPWR = 44 V	11713	12015	12316	Counts
		VVPWR = 44 V	42.89	44	45.10	V
	Powered Channel voltage conversion scale factor and accuracy	VVPWR - VDRAINn = 57 V	15175	15565	15955	Counts
		VVPWR - VDRAINn = 57 V	55.57	57	58.43	V
		VVPWR - VDRAINn = 44 V	11713	12015	12316	Counts
		VVPWR - VDRAINn = 44 V	42.89	44	45.10	V
δV/V_Channel	Voltage reading accuracy		–2.5		2.5	%
	Powered Channel current conversion scale factor and accuracy	Channel current = 770 mA	8431	8604	8776	Counts
		Channel current = 770 mA	754.5	770	785.4	mA
		Channel Current = 100 mA	1084	1118	1152	Counts
		Channel Current = 100 mA	97	100	103	mA
δI/I_Channel	Current reading accuracy	Channel Current = 100 mA	–3		3	%
δI/I_Channel	Current reading accuracy	Channel Current = 770 mA	–2		2	%
δR/R_Channel	Resistance reading accuracy	15 kΩ ≤ R_Channel ≤ 33 kΩ, C_Channel ≤ 0.25 µF	–7		7	%
I_bias	Sense Pin bias current	Channel ON or during class	–2.5		0	µA
GATE 1-8
V_GOH	Gate drive voltage	V_GATEn , I_GATE = –1 µA	10		12.5	V
I_GO-	Gate sinking current with Power-on Reset, OSS detected or channel turnoff command	V_GATEn = 5 V	60	100	190	mA
I_{GO short-}	Gate sinking current with channel short-circuit	V_GATEn = 5 V, V_SENn ≥ V_short (or V_short2X if 2X mode)	60	100	190	mA
I_GO+	Gate sourcing current	V_GATEn = 0 V, default selection	39	50	63	µA
t_{D_off_OSS}	Gate turnoff time from 1-bit OSS input	From OSS to VGATEn < 1 V, VSENn = 0 V, MbitPrty = 0	1		5	µs
t_{OSS_OFF}	Gate turnoff time from 3-bit OSS input	From Start bit falling edge to VGATEn < 1 V, VSENn = 0 V, MbitPrty = 1	72		104	µs
t_{P_off_CMD}	Gate turnoff time from channel turnoff command	From Channel off command (POFFn = 1) to V_GATEn < 1 V, V_SENn = 0 V			300	µs
t_{P_off_RST}	Gate turnoff time with /RESET	From /RESET low to V_GATEn < 1 V, V_SENn = 0 V	1		5	µs
DRAIN 1-8
V_PGT	Power-Good threshold	Measured at V_DRAINn	1	2.13	3	V
V_SHT	Shorted FET threshold	Measured at V_DRAINn	4	6	8	V
R_DRAIN	Resistance from DRAINn to VPWR	Any operating mode except during detection or while the Channel is ON, including in device RESET state	80	100	190	kΩ
AUTOCLASS
t_{Class_ACS}	Start of Autoclass Detection	Measured from the start of Class	90		100	ms
t_{AUTO_PSE1}	Start of Autoclass Power Measurement	Measured from the end of Inrush	1.4		1.6	s
t_{AUTO_PSE1}	Start of Autoclass Power Measurement	Measured from setting the MACx bit while channel is already powered			10	ms
t_AUTO	Duration of Autoclass Power Measurement		1.7	1.8	1.9	s
t_{AUTO_window}	Autoclass Power Measurement Sliding Window		0.15		0.3	s
P_AC	Autoclass Channel Power conversion scale factor and accuracy	VPWR = 52 V, VDRAINn = 0 V, Channel current = 770 mA	76	80	84	Counts
P_AC		VPWR = 50 V, VDRAINn = 0 V, Channel current = 100 mA	9	10	11
DETECTION
I_DISC	Detection current	First and 3rd detection points VVPWR – VDRAINn = 0 V	145	160	190	µA
I_DISC	Detection current	2nd and 4th detection points VVPWR – VDRAINn = 0 V	235	270	300	µA
ΔI_DISC	2nd – 1st detection currents	VVPWR - VDRAINn = 0 V	98	110	118	µA
V_{det_open}	Open circuit detection voltage	Measured as VVPWR – VDRAINn	23.5	26	29	V
R_{REJ_LOW}	Rejected resistance low range		0.86		15	kΩ
R_{REJ_HI}	Rejected resistance high range		33		100	kΩ
R_ACCEPT	Accepted resistance range		19	25	26.5	kΩ
R_SHORT	Shorted Channel threshold				360	Ω
R_OPEN	Open Channel Threshold		400			kΩ
t_DET	Detection Duration	Time to complete a detection	275	350	425	ms
t_{DET_BOFF}	Detect backoff pause between discovery attempts	VVPWR – VDRAINn > 2.5 V	300	400	500	ms
t_{DET_BOFF}	Detect backoff pause between discovery attempts	VVPWR – VDRAINn < 2.5 V	20		100	ms
t_{DET_DLY}	Detection delay	From command or PD attachment to Channel detection complete			590	ms
	Capacitance Measurement	Cport = 10uF	8.5	10	11.5	uF
CLASSIFICATION
V_CLASS	Classification Voltage	VVPWR – VDRAINn, VSENn ≥ 0 mV I_channel ≥ 180 µA	15.5	18.5	20.5	V
I_{CLASS_Lim}	Classification Current Limit	VVPWR – VDRAINn = 0 V	65	75	90	mA
I_{CLASS_TH}	Classification Threshold Current	Class 0-1	5		8	mA
		Class 1-2	13		16	mA
		Class 2-3	21		25	mA
		Class 3-4	31		35	mA
		Class 4-Class overcurrent	45		51	mA
t_LCE	Classification Duration (1st Finger)	From detection complete	95		105	ms
t_CLE2/3	Classification Duration (2nd & 3th Finger)	From Mark complete	6.5		12	ms
MARK
V_MARK	Mark Voltage	4 mA ≥ I_Channel ≥ 180 µA VVPWR – VDRAINn	7		10	V
I_{MARK_Lim}	Mark Sinking Current Limit	VVPWR – VDRAINn = 0 V	60	75	90	mA
t_ME	Mark Duration		6		12	ms
DC DISCONNECT
V_IMIN	DC disconnect threshold		0.8	1.3	1.8	mV
t_MPDO	PD Maintain Power signature dropout time limit	TMPDO = 00	320		400	ms
		TMPDO = 01	75		100	ms
		TMPDO = 10	150		200	ms
		TMPDO = 11	600		800	ms
t_MPS	PD Maintain Power Signature time for validity			2.5	3	ms
PORT POWER POLICING
δP_CUT/P_CUT	PCUT tolerance	< 15 W	0	6	12	%
δP_CUT/P_CUT	PCUT tolerance	≥ 15 W	0	4	8	%
t_OVLD	PCUT time limit	TOVLD = 00	50		70	ms
		TOVLD = 01	25		35
		TOVLD = 10	100		140
		TOVLD = 11	200		280
PORT CURRENT INRUSH
V_Inrush	IInrush limit, ALTIRNn = 0	VVPWR – VDRAINn = 1 V	19	30	41	mV
		VVPWR – VDRAINn = 10 V	19	30	41
		VVPWR – VDRAINn = 15 V	33	44	55
		VVPWR – VDRAINn = 30 V	80		90
		VVPWR – VDRAINn = 55 V	80		90
	IInrush limit, ALTIRNn = 1	VVPWR – VDRAINn = 1 V	19	30	41
		VVPWR – VDRAINn = 10 V	36	47	58
		VVPWR – VDRAINn = 15 V	53	64	75
		VVPWR – VDRAINn = 30 V	80		90
		VVPWR – VDRAINn = 55 V	80		90
t_START	Maximum current limit duration in start-up	TSTART = 00	50		70	ms
		TSTART = 01	25		35
		TSTART = 10	100		140
PORT CURRENT FOLDBACK
V_LIM	ILIM 1X limit, 2xFB = 0 and ALTFBn = 0	VDRAINn = 1 V	80		90	mV
		VDRAINn = 15 V	80		90
		VDRAINn = 30 V	51	58	65
		VDRAINn = 50 V	23	30	37
	ILIM 1X limit, 2xFB = 0 and ALTFBn = 1	VDRAINn = 1 V	80		90
		VDRAINn = 25 V	80		90
		VDRAINn = 40 V	45	51	57
		VDRAINn = 50 V	23	30	37
V_LIM2X	ILIM 2X limit, 2xFB = 1 and ALTFBn = 0	VDRAINn = 1 V	245	250	262	mV
		VDRAINn = 10 V	164	180	196
		VDRAINn = 30 V	51	58	64
		VDRAINn = 50 V	23	30	37
	ILIM 2X limit, 2xFB = 1 and ALTFBn = 1	VDRAINn = 1 V	245	250	262
		VDRAINn = 20 V	139	147	155
		VDRAINn = 40 V	45	51	57
		VDRAINn = 50 V	23	30	37
t_LIM	ILIM time limit	2xFBn = 0	55	60	65	ms
	2xFBn = 1	TLIM = 00	55	60	65
		TLIM = 01	15	16	17
		TLIM = 10	10	11	12
		TLIM = 11	6	6.5	7
SHORT CIRCUIT DETECTION
V_short	I_SHORT threshold in 1X mode and during inrush		205		245	mV
V_short2X	I_SHORT threshold in 2X mode		280		320	mV
t_{D_off_SEN}	Gate turnoff time from SENn input	2xFBn = 0, VDRAINn = 1 V From VSENn pulsed to 0.425 V.			0.9	µs
t_{D_off_SEN}	Gate turnoff time from SENn input	2xFBn = 1, VDRAINn = 1 V From VSENn pulsed to 0.62 V.			0.9	µs
CURRENT FAULT RECOVERY (BACKOFF) TIMING
t_ed	Error delay timing. Delay before next attempt to power a channel following power removal due to error condition	P_CUT , I_LIM or I_Inrush fault semiauto mode	0.8	1	1.2	s
δI_fault	Duty cycle of I_channel with current fault		5.5		6.7	%
THERMAL SHUTDOWN
	Shutdown temperature	Temperature rising	135	146		°C
	Hysteresis			7		°C
DIGITAL I/O (SCL, SDAI, A1-A4, /RESET, OSS unless otherwise stated)
V_IH	Digital input High		2.1			V
V_IL	Digital input Low				0.9	V
V_{IT_HYS}	Input voltage hysteresis		0.17			V
V_OL	Digital output Low	SDAO at 9mA			0.4	V
V_OL	Digital output Low	/INT at 3mA			0.4	V
R_pullup	Pullup resistor to VDD	/RESET, A1-A4, TEST0	30	50	80	kΩ
R_pulldown	Pulldown resistor to DGND	OSS, TEST1, TEST2	30	50	80	kΩ
t_{FLT_INT}	Fault to /INT assertion	Time to internally register an Interrupt fault, from Channel turn off		50	500	µs
T_RESETmin	/RESET input minimum pulse width				5	µs
T_{bit_OSS}	3-bit OSS bit period	MbitPrty = 1	24	25	26	µs
t_{OSS_IDL}	Idle time between consecutive shutdown code transmission in 3-bit mode	MbitPrty = 1	48	50		µs
t_{r_OSS}	Input rise time of OSS in 3-bit mode	0.8 V → 2.3 V, MbitPrty = 1	1		300	ns
t_{f_OSS}	Input fall time of OSS in 3-bit mode	2.3 V → 0.8 V, MbitPrty = 1	1		300	ns
I2C TIMING REQUIREMENTS
t_POR	Device power-on reset delay				20	ms
f_SCL	SCL clock frequency		10		400	kHz
t_LOW	LOW period of the clock		0.5			µs
t_HIGH	HIGH period of the clock		0.26			µs
t_fo	SDAO output fall time	SDAO, 2.3 V → 0.8 V, Cb = 10 pF, 10 kΩ pull-up to 3.3 V	10		50	ns
t_fo	SDAO output fall time	SDAO, 2.3 V → 0.8 V, Cb = 400 pF, 1.3 kΩ pull-up to 3.3 V	10		50	ns
C_I2C	SCL capacitance				10	pF
C_{I2C_SDA}	SDAI, SDAO capacitance				6	pF
t_SU,DATW	Data setup tme (Write operation)		50			ns
t_HD,DATW	Data hold time (Write operation)		0			ns
t_HD,DATR	Data hold time (Read operation)		150		400	ns
t_fSDA	Input fall times of SDAI	2.3 V → 0.8 V	20		120	ns
t_rSDA	Input rise times of SDAI	0.8 V → 2.3 V	20		120	ns
t_r	Input rise time of SCL	0.8 V → 2.3 V	20		120	ns
t_f	Input fall time of SCL	2.3 V → 0.8 V	20		120	ns
t_BUF	Bus free time between a STOP and START condition		0.5			µs
t_HD,STA	Hold time After (Repeated) START condition		0.26			µs
t_SU,STA	Repeated START condition setup time		0.26			µs
t_SU,STO	STOP condition setup time		0.26			µs
t_DG	Suppressed spike pulse width, SDAI and SCL		50			ns
t_{WDT_I2C}	I2C Watchdog trip delay		1.1	2.2	3.3	sec