The average power dissipation within the eFuse during power up with a capacitive load can be calculated using Equation 3.

Equation 3.

System designs requiring to charge large output capacitors rapidly may result in an operating point that exceeds the power dissipation versus time boundary limits of the device defined by Figure 6-7 characteristic curve. This may result in increase in junction temperature beyond the device's maximum allowed junction temperature. To keep the junction temperature within the operating range, the thermal regulation control loop regulates the junction temperature at T_{(J_REG)} , 145°C (typical) by controlling the inrush current profile and thereby limiting the power dissipation within the device automatically. An internal 1.3 sec (typical), t_{(Treg_timeout)} timer starts from the instance the thermal regulation operation kicks in. If the output does not power up within this time then the internal FET is turned OFF. Subsequent operation of the device depends on the MODE configuration (Auto-Retry or latch OFF) setting as per the Table 8-2. The maximum time-out of 1.3 sec (typical) in thermal regulation loop operation ensures that the device and the system board does not heat up during steady fault conditions such as wake up with output short-circuit. This scheme ensures reliable power up operation.

Thermal regulation control loop is internally enabled during power up by V_(IN), UVLO cycling and turn ON using SHDN control. Figure 8-2 illustrates performance of the device operating in thermal regulation loop during power up by V_(IN) with a large output capacitor. The Thermal regulation loop gets disabled internally after the power up sequence when the internal FET's gate gets fully enhanced or when the t_{(Treg_timeout)} of 1.3 sec (typical) time is elapsed.

CdVdT = Open	VIN = 35 V	RILIM = 4.02 kΩ

Figure 8-2 Thermal Regulation Loop Response During Power Up With 4.7-mF Capacitive Load