The UCC28781-Q1 uses an external NTC resistor (R_NTC) tied to the FLT pin to program a thermal shutdown temperature near the hotspot of the converter. The NTC shutdown threshold (V_NTCTH) of 0.5 V with an internal 50-μA current source flowing through R_NTC results in a 10-kΩ thermistor shutdown threshold. If the NTC resistance stays lower than 10 kΩ for more than 50 μs, an OTP fault event is triggered. The 50-μs delay (t_FLT(NTC)) allows a filter capacitor (C_FLT) to be placed between the FLT pin and the AGND pin, when the NTC resistor is located far away from the controller but close to the hot spot. To avoid the OTP fault from false trigger as RUN goes high, C_FLT should be designed to allow V_FLT increased above V_NTCTH within t_FLT(NTC). On the other hand, if the NTC resistor is close to the controller and there is no potential noise coupling path to the sensing traces, C_FLT is not needed.

For auto-recovery mode, the 0.5-V threshold is increased to 1.15 V after the OTP fault, so the NTC resistance has to increase above 23 kΩ to reset the OTP fault. This threshold change provides a safe temperature hysteresis to help the hot-spot temperature cool down before the next V_O restart attempt, reducing the thermal stress to the components. If the FLT pin is not used, the pin can be left floating but can not be connected to REF pin, since the line OVP will be falsely triggered.

The thermal issue in the heavy output load condition is the main design consideration for OTP, and the heavy load operating mode, AAM, allows the controller to stay in the run state continuously, so the 50-μs delay allows V_FLT to trigger OTP. Based on the practical BUR-pin setting, 50% to 60% load is operated in AAM. The 50-μA current source is disabled in the burst off time of the light load modes such as ABM, LPM, SBP1, and SBP2, in order to save standby power. However, when the run state becomes shorter than the 50-μs in these modes but the current source is disabled in the wait state, the OTP will not be able to trigger because there is not enough time to detect the fault. Therefore, if certain design considerations still require the OTP to be armed in light load modes, a second OTP configuration can be considered by reusing the 4.5-V threshold of input OVP. As shown in Figure 7-40, the upper NTC resistor and the lower resistor form a resistor divider from the REF pin to the FLT pin. The 750-μs delay is independent to the wait state condition of controller, so the OTP fault can still be triggered in the light load mode. This configuration provides auto-recovery mode only.

Figure 7-40 Two Connections to Implement OTP on the FLT Pin

Figure 7-41 OTP Timing Diagram for a NTC between the FLT Pin and AGND Pin