The VCC pin powers the UCC25800-Q1 transformer driver. When the VCC pin voltage is below the UVLO rising threshold (UVLO_R), the VREG pin 5-V regulator is disabled (VREG = 0 V). After the VCC pin voltage exceeds UVLO_R, the 5-V regulator is enabled and VREG pin rises, while the DIS/FLT pin is internally pulled low through an internal 750-μA current source, (DIS/FLT = 0 V). When the VREG exceeds 4.5 V (VREG_OK), the DIS/FLT pin is released. If the DIS/FLT pin is not pulled low externally, it rises to VREG pin voltage level via an internal 100-kΩ pull up resistor. When DIS/FLT pin voltage exceeds the rising enable threshold (EN_TH), the internal regulators and references are turned on and the transformer driver reads the Thevenin resistance on the OC/DT pin to set the overcurrent protection (OCP) thresholds. After this process completes, the faults are checked and if they are all cleared, the oscillator is enabled and the power stage starts switching. The time to complete this process is approximately 500 μs.

If a fault is detected, the transformer driver activates the internal pull-down current source on the DIS/FLT pin, the power stage stops switching, and the device outputs the fault code.

The rise time of the DIS/FLT pin depends on the external loading on the pin. An external pull-up can be added to the pin if there is concern over noise immunity. The values are specified in Section 8.3.6.

When the VCC pin voltage is above the UVLO_R threshold and DIS/FLT pin is pulled low externally the transformer driver remains disabled with IVCC_DIS = 660 µA.

If after a completed power-up sequence, VCC falls below the UVLO falling threshold (UVLO_F), the power stage switching is immediately stopped. The VREG pin voltage regulator is disabled making the VREG pin voltage fall.

The VCC pin current is a combination of the IC bias current and the power stage current. It is important to have a low ESL bypass capacitor to minimize the current loop among this capacitor and VCC, GND pins. Refer to Section 11 for details.