米6体育平台手机版

ZHCSO49C May 2021 – March 2023 TPS629210-Q1

PRODUCTION DATA

8.3.3 Selectable V_O Operation (VSET and Internal Voltage Divider)

If the device is configured to VSET operation, the device interprets the VSET pin value following the MODE/S-CONF readout (see Figure 8-3). There is no further interpretation of the VSET pin during operation and the output voltage cannot be changed afterward without toggling the EN pin.

Figure 8-3 shows the typical schematic for this configuration, where V_O is directly sensed at the VOS pin of the device. V_O is sensed only through the VOS pin by an internal resistor divider. The target V_O is programmed by an external resistor connected between VSET and GND (see Table 8-2).

Figure 8-3 Selectable V_O Operation Schematic

Table 8-2 VSET Selection Table

VSET #	Resistor Value [Ω]⁽¹⁾	Target V_O [V]
1	GND	1.2
2	4.87 k	0.4
3	6.04 k	0.6
4	7.50 k	0.8
5	9.31 k	0.85
6	11.50 k	1.0
7	14.30 k	1.1
8	17.80 k	1.25
9	22.10 k	1.3
10	27.40 k	1.35
11	34.00 k	1.8
12	42.20 k	1.9
13	52.30 k	2.5
14	64.90 k	3.8
15	80.60 k	5.0
16	100.00 k	5.1
17	124.00 k	5.5
18	249.00 k or larger/open	3.3

(1) E96 Resistor Series, 1% accuracy, temperature coefficient better or equal to ±200 ppm/°C

8.3.3 Selectable VO Operation (VSET and Internal Voltage Divider)

8.3.3 Selectable V_O Operation (VSET and Internal Voltage Divider)