The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA controller has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory when the peripheral is ready to transfer more data.

Some features of the µDMA controller include the following (this is not an exhaustive list):

• Highly flexible and configurable channel operation of up to 32 channels
• Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
  peripheral-to-peripheral
• Data sizes of 8, 16, and 32 bits
• Ping-pong mode for continuous streaming of data