Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted)
| PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
| Flash sector size |
|
|
8 |
|
KB |
| Supported flash erase cycles before failure, single-bank(1)(5) |
|
30 |
|
|
k Cycles |
| Supported flash erase cycles before failure, single sector(2) |
|
60 |
|
|
k Cycles |
| Maximum number of write operations per row before sector erase(3) |
|
|
|
83 |
Write Operations |
| Flash retention |
105 °C |
11.4 |
|
|
Years at 105 °C |
| Flash sector erase current |
Average delta current |
|
9.5 |
|
mA |
| Flash sector erase time(4) |
Zero cycles |
|
10 |
|
ms |
| 30k cycles |
|
|
4000 |
ms |
| Flash write current |
Average delta current, 4 bytes at a time |
|
5.2 |
|
mA |
| Flash write time(4) |
4 bytes at a time |
|
21.6 |
|
µs |
(1) A full bank erase is counted as a single erase cycle on each sector. If both flash banks are always cycled simultaneously they can be cycled 30K times each. Alternatively, the banks can be cycled a total of 30K times, e.g. the main bank X times and the second bank Y times (X+Y=30K)
(2) Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k cycles
(3) Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum per write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum number of write operations per row is reached.
(4) This number is dependent on Flash aging and increases over time and erase cycles
(5) Aborting flash during erase or program modes is not a safe operation.