The CAN bus has two logical states during operation: recessive and dominant. See Figure 9-9.

A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD and RXD pins. A recessive bus state occurs when the bus is biased to one half of the CAN transceiver supply voltage via the high resistance internal input resistors (R_IN) of the receiver and corresponds to a logic high on the TXD and RXD pins.

A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a dominant bit at the same time during arbitration, and in this case the differential voltage of the CAN bus will be greater than the differential voltage of a single CAN driver. The TCAN1162-Q1 CAN transceiver implements low-power standby and sleep modes which enables a third bus state where the bus pins are biased to ground via the high resistance internal resistors of the receiver.

Figure 9-9 Bus States