ZHCSOO3A May   2021  – December 2021

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configurations and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 ESD Ratings IEC Specification
    4. 7.4 Recomended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Power Supply Characteristics
    7. 7.7 Electrical Characteristics
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  VSUP Pin
      2. 9.3.2  VFLT Pin
      3. 9.3.3  Digital Inputs and Outputs
        1. 9.3.3.1 TXD Pin
        2. 9.3.3.2 RXD Pin
        3. 9.3.3.3 TS Pin
      4. 9.3.4  Digital Control and Timing
      5. 9.3.5  VIO Pin
      6. 9.3.6  GND
      7. 9.3.7  INH Pin
      8. 9.3.8  WAKE Pin
      9. 9.3.9  CAN Bus Pins
      10. 9.3.10 Local Faults
        1. 9.3.10.1 TXD Dominant Timeout (TXD DTO)
        2. 9.3.10.2 Thermal Shutdown (TSD)
        3. 9.3.10.3 Under/Over Voltage Lockout
        4. 9.3.10.4 Unpowered Devices
        5. 9.3.10.5 Floating Terminals
        6. 9.3.10.6 CAN Bus Short Circuit Current Limiting
        7. 9.3.10.7 Sleep Wake Error Timer
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operating Mode Description
        1. 9.4.1.1 Normal Mode
        2. 9.4.1.2 Standby Mode
        3. 9.4.1.3 Sleep Mode
          1. 9.4.1.3.1 Remote Wake Request via Wake-Up Pattern (WUP)
          2. 9.4.1.3.2 Local Wake-Up (LWU) via WAKE Input Terminal
        4. 9.4.1.4 Fail-safe Mode
      2. 9.4.2 CAN Transceiver
        1. 9.4.2.1 CAN Transceiver Operation
        2. 9.4.2.2 CAN Transceiver Modes
          1. 9.4.2.2.1 CAN Off Mode
          2. 9.4.2.2.2 CAN Autonomous: Inactive and Active
          3. 9.4.2.2.3 CAN Active
        3. 9.4.2.3 Driver and Receiver Function Tables
        4. 9.4.2.4 CAN Bus States
  10. 10Application Information
    1. 10.1 Application Information Disclaimer
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Bus Loading, Length and Number of Nodes
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 CAN Termination
    3. 10.3 Application Curves
  11. 11Power Supply Requirements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 术语表
  14. 14Mechanical, Packaging, and Orderable Information

7.8 Switching Characteristics

Over recomended operating conditions with TJ = -40°C to 150°C, unless otherwise noted. All typical values are taken at 25°C, VSUP = 12 V, VIO = 3.3 V and RL = 60 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply Switching Characteristics
tPOWER_UP CAN supply power up time CFLT = 10 µF


nSLP = 5 V
See Figure 8-7



 1.8 4 ms
tUV(SUP) VSUP filter time (rising and falling) 4 25 µs
tUV(FLT) Undervoltage detection delay time CAN active to CAN autonomous: active or inactive 4 25 µs
tUVIO VIO filter time (rising and falling) 8 12 µs
Device Switching Characteristics
tUVIO(SLP) Undervoltage detection delay time standby mode to sleep mode 200 350 ms
tWK_FILTER Bus time to meet filtered bus requirments for wakeup request
See Figure 9-4		 0.5 1.8 µs
tWK_TIMEOUT Bus wakeup timeout value 0.8 2 ms
tSILENCE Time out for bus inactivity 0.9 1.2 s
tINACTIVE Hardware timer for failsafe and power up inactivity(1) 3 4 5 min
tBIAS Time from the start of a dominant-recessive-dominant sequence until Vsym ≥ 0.1 Each phase: 6 μs
See Figure 8-9		 250 µs
tCAN(ACTIVE) Time from swtiching to CAN active mode to TS pin transitioning high VFLT > UVFLT(R)

VIO > UVIO(R)
nSLP = VIO		 25 us
tPROP(LOOP1) Total loop delay, driver input (TXD) to receiver output (RXD)
Recessive to dominant		 RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
See Figure 8-4		 100 160 ns
tPROP(LOOP2) Total loop delay, driver input (TXD) to receiver output (RXD)
Dominant to recessive		 120 175 ns
tnSLP(fltr) nSLP pin filter time Sleep pin filter time 2.5 7.5 µs
tSLP Mode change time Low time  required on nSLP to enter sleep mode 20 35 µs
tmode_slp_stb WUP or LWU event to INH asserted high, see 50 µs
Driver Switching Characteristics
tpHR Propagation delay time, high TXD to driver recessive RL = 60 Ω, CL = 100 pF, RCM = open
See Figure 8-2		 20 35 70 ns
tpLD Propagation delay time, low TXD to driver dominant 15 40 70 ns
tsk(p) Pulse skew (|tpHR - tpLD|) 10 20 ns
tR Differential output signal rise time 40 ns
tF Differential output signal fall time 45 ns
tTXD_DTO Dominant timeout RL = 60 Ω, CL = open
See Figure 8-5, TXD = 0 V		 1.2 3.8 ms
Receiver Switching Characteristics
tpRH Propagation delay time, bus recessive input to high RXD CL(RXD) = 15 pF
See Figure 8-3		 25 80 140 ns
tpDL Propagation delay time, bus dominant input to RXD low output 20 50 110 ns
tR Output signal rise time (RXD) 8 ns
tF Output signal fall time (RXD) 5 ns
WAKE Characteristics
tWAKE Time required for INH pin to go high after an local wake event occurs on the WAKE pin 40 µs
CAN FD Timing Characteristics
tBIT(BUS) Bit time on CAN bus output pins with tBIT(TXD) = 500 ns VIO > 1.8V RL = 60 Ω, CL = 100 pF
CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 8-4		 435 530 ns
Bit time on CAN bus output pins with tBIT(TXD) = 200 ns 155 210 ns
Bit time on CAN bus output pins with tBIT(TXD) = 125 ns 80 140 ns
tBIT(BUS) Bit time on CAN bus output pins with tBIT(TXD) = 500 ns VIO ≤ 1.8V RL = 60 Ω, CL = 100 pF
CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 8-4		 435 530 ns
Bit time on CAN bus output pins with tBIT(TXD) = 200 ns 155 215 ns
Bit time on CAN bus output pins with tBIT(TXD) = 125 ns 80 140 ns
tBIT(RXD) Bit time on RXD output pins with tBIT(TXD) = 500 ns RL = 60 Ω, CL = 100 pF
CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 8-4		 400 550 ns
Bit time on RXD output pins with tBIT(TXD) = 200 ns 120 220 ns
Bit time on RXD output pins with tBIT(TXD) = 125 ns 80 135 ns
ΔtREC Receiver timing symmetry with tBIT(TXD) = 500 ns RL = 60 Ω, CL = 100 pF
CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 8-4		 -65 40 ns
Receiver timing symmetry with tBIT(TXD) = 200 ns -45 15 ns
Receiver timing symetry with tBIT(TXD) = 125 ns -40 10 ns
(1) Timer is reset when the CAN bus changes states.
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