The dynamic performance of the TPS7A21 is dependent on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the TPS7A21.

Best performance is achieved by placing C_IN and C_OUT on the same side of the PCB as the TPS7A21, and as close to the package as practical. The ground connections for C_IN and C_OUT must be back to the TPS7A21 ground pin using as wide and short a copper trace as practical.

Connections using long trace lengths, narrow trace widths, or connections through vias must be avoided. These connections add parasitic inductances and resistance that results in inferior performance, especially during transient conditions.