Three-wire mode is used for applications that require higher levels of power transfer or the shortest propagation delay TPSI3050-Q1 can offer. VDDP is supplied independently from the EN pin by a low output impedance external supply that can deliver the required power. In this mode, power from the primary side to the secondary side always occurs regardless of the state of the EN pin. Setting the EN pin logic high or low asserts or de-asserts VDRV, thereby enabling or disabling the external switch, respectively. Figure 8-1 shows the basic setup required for three-wire mode operation which requires EN, VDDP, and VSSP signals. EN can be driven up to 5.5 V which is normally driven from the circuitry residing on the same rail as VDDP. In this example, the TPSI3050-Q1 is being used to drive back-to-back MOSFETs in a common-source configuration. C_VDDP provides the required decoupling capacitance for the VDDP supply rail of the device. C_DIV1 and C_DIV2 provide the required decoupling capacitances of the VDDH and VDDM supply rails that provide the peak current to drive the external MOSFETs.

Figure 8-2 and Figure 9-10 show the basic operation from start-up to steady-state conditions. Figure 8-2 shows operation using standard enable of the TPSI3050-Q1. After power up, the TPSI3050-Q1 begins to transfer power from VDDP to the secondary side for a fixed time period (25-μs typical) at a duty cycle rate determined by R_PXFR, which begins to charge up the VDDH (and VDDM) secondary side rails. Power transfer continues as long as VDDP is present. The time required to fully charge VDDH depends on several factors including the values of VDDP, C_DIV1, C_DIV2, R_PXFR, and the overall power transfer efficiency. When the application drives the EN pin to a logic high, the TPSI3050-Q1 signals information from the primary side to the secondary side to assert VDRV and drive it high. Similarly, setting EN pin to a logic low causes VDRV to be driven low. Figure 9-10 shows operation using one-shot enable of the TPSI3050S-Q1. The start-up behavior is identical. In one-shot enable, when the application drives the EN pin to a logic high, VDRV is asserted high (t_{HI_VDRV}), then is automatically asserted low by the TPSI3050S-Q1. To assert VDRV high again, the EN pin must transition low first, followed by a transition high.

Figure 8-1 Three-Wire Mode Simplified Schematic

Figure 8-2 Three-Wire Mode with TPSI3050-Q1 (Standard Enable)

Figure 8-3 Three-Wire Mode with TPSI3050S-Q1 (One-shot Enable)

To reduce average power, the TPSI3050-Q1 transfers power from the primary side to the secondary side in a burst fashion. The period of the burst is fixed while the burst on time is programmable by selecting one of seven appropriate resistor values, R_PXFR, from the PXFR to VSSP pins, thereby changing the duty cycle of the power converter. This action provides flexibility in the application, allowing tradeoffs in power consumed versus power delivered. Higher power converter settings increase the burst on time which, in turn, increases average power consumed from the VDDP supply and increases the amount of power transferred to the secondary side VDDH and VDDM supplies. Similarly, lower power converter settings decrease the burst on time which, in turn, decreases average power consumed from the VDDP supply and decreases the amount of power transferred to the secondary side.

Table 8-1 summarizes the three-wire mode power transfer selection.