The DAC11001B incorporates two internal POR circuits for the DV_DD, AV_DD, IOV_DD, V_CC, and V_SS supplies. The POR signals are ANDed together, so that all supplies must be at the minimum specified values for the device to not be in a reset condition. These POR circuits initialize internal registers, as well as set the analog outputs to a known state, all while the device supplies are ramping. All registers are reset to default values. The DAC11001B powers on with the DAC registers set to zero scale. The DAC output can be powered down by writing 1 to PDN (bit 4, address 02h). Typically, the POR function can be ignored as long as the device supplies power up and maintain the specified minimum voltage levels. However, a supply drop or brownout can trigger an internal POR reset event. Figure 7-2 represents the internal POR threshold levels for the DV_DD, AV_DD, IOV_DD, V_CC, and V_SS supplies.

Figure 7-2 Relevant Voltage Levels for the POR Circuit

For the DV_DD supply, no internal POR occurs for nominal supply operation from 2.7 V (supply minimum) to 5.5 V (supply maximum). For a DV_DD supply region between 2.5 V (undefined operation threshold) and 1.6 V (POR threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For a DV_DD supply less than 1.6 V (POR threshold), the internal POR resets as long as the supply voltage is less than 1.6 V for approximately 1 ms.

For the AV_DD supply, no internal POR occurs for nominal supply operation from 4.5 V (supply minimum) to 5.5 V (supply maximum). For an AV_DD supply region between 4.1 V (undefined operation threshold) and 3.3 V (POR threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For an AV_DD supply less than 3.3 V (POR threshold), the internal POR resets as long as the supply voltage is less than 3.3 V for approximately 1 ms.

For the V_CC supply, no internal POR occurs for nominal supply operation from 8 V (supply minimum) to 36 V (supply maximum). For V_CC supply voltages between 7.5 V (undefined operation threshold) to 6 V (POR threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For a V_CC supply less than 6 V (POR threshold), the internal POR resets as long as the supply voltage is less than 6 V for approximately 1 ms.

For the V_SS supply, no internal POR occurs for nominal supply operation from –3 V (supply minimum) to –18 V (supply maximum). For V_SS supply voltages between –2.7 V (undefined operation threshold) to –1.8 V (POR threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For a V_SS supply greater than –1.8 V (POR threshold), the internal POR resets as long as the supply voltage is greater than –1.8 V for approximately 1 ms.

For the IOV_DD supply, no internal POR occurs for nominal supply operation from 1.8 V (supply minimum) to 5.5 V (supply maximum). For IOV_DD supply voltages between 1.5 V (undefined operation threshold) and 0.8 V (POR threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For an IOV_DD supply less than 0.8 V (POR threshold), the internal POR resets as long as the supply voltage is less than 0.8 V for approximately 1 ms.

In case the DV_DD, AV_DD, IOV_DD, V_CC, or V_SS supply drops to a level where the internal POR signal is indeterminate, power cycle the device followed by a software reset.