ZHCSPG5 December 2021 DAC11001B
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Timing Requirements: Write, 4.5 V ≤ DVDD ≤ 5.5 V
- 6.7 Timing Requirements: Write, 2.7 V ≤ DVDD < 4.5 V
- 6.8 Timing Requirements: Read and Daisy-Chain Write, 4.5 V ≤ DVDD ≤ 5.5 V
- 6.9 Timing Requirements: Read and Daisy-Chain Write, 2.7 V ≤ DVDD < 4.5 V
- 6.10 Timing Diagrams
- 6.11 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Map
- 7.6.1 NOP Register (address = 00h) [reset = 0x000000h for bits [23:0]]
- 7.6.2 DAC-DATA Register (address = 01h) [reset = 0x000000h for bits [23:0]]
- 7.6.3 CONFIG1 Register (address = 02h) [reset = 004C80h for bits [23:0]]
- 7.6.4 DAC-CLEAR-DATA Register (address = 03h) [reset = 000000h for bits [23:0]]
- 7.6.5 TRIGGER Register (address = 04h) [reset = 000000h for bits [23:0]]
- 7.6.6 STATUS Register (address = 05h) [reset = 000000h for bits [23:0]]
- 7.6.7 CONFIG2 Register (address = 06h) [reset = 000040h for bits [23:0]]
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7.3.1 Digital-to-Analog Converter Architecture
The DAC11001B provides 20-bit monotonic outputs using an R2R ladder architecture. The DAC output ranges between VREFNF and VREFPF based on the 20-bit DAC data, as described in Equation 1:
Equation 1. 
where
- CODE is the decimal equivalent of the DAC-DATA loaded to the DAC.
- N is the bits of resolution.
- VREFPF, VREFNF is the reference voltage (positive and negative).