ZHCSPG5 December 2021 DAC11001B
PRODUCTION DATA
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
fSCLK | SCLK frequency | 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 | 10 | MHz | ||
1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 | 20 | |||||
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 | 15 | |||||
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 | 30 | |||||
tSCLKHIGH | SCLK high time | 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 | 50 | ns | ||
1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 | 25 | |||||
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 | 33 | |||||
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 | 16 | |||||
tSCLKLOW | SCLK low time | 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 | 50 | ns | ||
1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 | 25 | |||||
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 | 33 | |||||
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 | 16 | |||||
tSDIS | SDI setup, 1.7 V ≤ IOVDD < 2.7 V | 13 | ns | |||
SDI setup, 2.7 V ≤ IOVDD ≤ 5.5 V | 8 | |||||
tSDIH | SDI hold, 1.7 V ≤ IOVDD < 2.7 V | 13 | ns | |||
SDI hold, 2.7 V ≤ IOVDD ≤ 5.5 V | 8 | |||||
tCSS | SYNC falling edge to SCLK falling edge, 1.7 V ≤ IOVDD < 2.7 V | 30 | ns | |||
SYNC falling edge to SCLK falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V | 20 | |||||
tCSH | SCLK falling edge to SYNC rising edge, 1.7 V ≤ IOVDD < 2.7 V | 15 | ns | |||
SCLK falling edge to SYNC rising edge, 2.7 V ≤ IOVDD ≤ 5.5 V | 10 | |||||
tCSHIGH | SYNC high time, 1.7 V ≤ IOVDD < 2.7 V | 55 | ns | |||
SYNC high time, 2.7 V ≤ IOVDD ≤ 5.5 V | 50 | |||||
tCSIGNORE | SCLK falling edge to SYNC ignore, 1.7 V ≤ IOVDD < 2.7 V | 10 | ns | |||
SCLK falling edge to SYNC ignore, 2.7 V ≤ IOVDD ≤ 5.5 V | 5 | |||||
tLDACSL | Synchronous update: SYNC rising edge to LDAC falling edge, 1.7 V ≤ IOVDD < 2.7 V |
50 | ns | |||
Synchronous update: SYNC rising edge to LDAC falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V |
50 | |||||
tLDACW | LDAC low time, 1.7 V ≤ IOVDD < 2.7 V | 20 | ns | |||
LDAC low time, 2.7 V ≤ IOVDD ≤ 5.5 V | 20 | |||||
tCLRW | CLR low time, 1.7 V ≤ IOVDD < 2.7 V | 20 | ns | |||
CLR low time, 2.7 V ≤ IOVDD ≤ 5.5 V | 20 | |||||
tSDODLY | SCLK rising edge to SDO valid data, 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 | 0 | 35 | ns | ||
SCLK rising edge to SDO valid data, 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 | 0 | 25 | ||||
SCLK falling edge to SDO valid data, 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 | 0 | 35 | ||||
SCLK falling edge to SDO valid data, 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 | 0 | 25 | ||||
tSDOZ | SYNC rising edge to SDO HiZ, 1.7 V ≤ IOVDD < 2.7 V | 0 | 20 | ns | ||
SYNC rising edge to SDO HiZ, 2.7 V ≤ IOVDD ≤ 5.5 V | 0 | 20 |