Layout is a critical portion of good power supply
design. See the Layout Example section for a PCB layout example.
It is recommended to include a large topside area filled with ground. This top layer ground area should be connected to the internal ground layer(s) using vias at the input bypass capacitor, the output filter capacitor, and directly under the TPS7H4003-SEP device to provide a thermal path from the exposed thermal pad land to ground. For operation at full rated load, the top side ground area together with the internal ground plane must provide adequate heat dissipating area.
The GND pin should be tied directly to the thermal pad under the IC.
There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the PVIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric.
Care should be taken to minimize the loop area formed by the bypass capacitor connections, the PVIN pins, and the ground connections.
The VIN pin must also be bypassed to ground using a low ESR ceramic capacitor with X5R or X7R dielectric. Make sure to connect this capacitor to the quieter analog ground trace rather than the power ground trace of the PVIN bypass capacitor.
Since the PH connection is the switching node, the output inductor should be located close to the PH pins and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
The output filter capacitor ground should use the same power ground trace as the PVIN input bypass capacitor. Try to minimize this conductor length while maintaining adequate width.
It is critical to keep the feedback trace away from inductor EMI and other noise sources. Run the feedback trace as far from the inductor, phase (PH) node, and noisy power traces as possible. Avoid routing this trace directly under the output inductor if possible. If not possible, ensure that the trace is routed on another layer with a ground layer separating the trace and inductor.
Keep the resistive divider used to generate VSENSE voltage as close to the device pin as possible in order to reduce noise pickup.
The RT and COMP pins are sensitive to noise as well, so components around these pins should be located as close as possible to the IC and routed with minimal lengths of trace.
Make all of the power (high current) traces as short, direct, and thick as possible.
It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline.