The LMK1D1208I is a low-additive jitter, I²C-programmable, LVDS output clock buffer that uses CMOS transistors to control the output current. Therefore, proper biasing and termination are required to ensure correct operation of the device and to maximize signal integrity. The LMK1D1208I also includes status and control registers for configuring the different modes in the device.

The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the receiver end. Either DC-coupled termination or AC-coupled termination can be used for LVDS outputs. TI recommends placing a termination resistor close to the receiver. If the receiver is internally biased to a voltage different than the output common-mode voltage of the LMK1D1208I, AC coupling must be used.If the LVDS receiver has internal 100-Ω termination, external termination must be omitted.