ZHCSPZ0A february 2022 – june 2023 LMK1D1208I
PRODUCTION DATA
The LMK1D1208I has an input stage that accepts up to two clock inputs and can be configured as either a 2:1 mux or as a dual bank. When configured as a 2:1 mux, the LMK1D1208I device can select one of the two clock inputs and then distribute it to the eight LVDS output pairs. In the dual bank mode, the LMK1D1208I can assign each clock input to fan out four LVDS output pairs per bank. Refer to the Device Functional Modes for how to configure the two input stages.
Unused inputs can be left floating to reduce overall component cost. Both AC and DC coupling schemes can be used with the LMK1D1208I to provide greater system flexibility.